Altera Corp EP1K100FC256-3

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Item Description: FPGA ACEX 1K Family 100K Gates 4992 Cells 200MHz CMOS Tech

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®
Altera Corporation 1
ACEX 1K
Programmable Logic Device Family
May 2003, ver. 3.4 Data Sheet
DS-ACEX-3.4
Development
13
Tools
Features...
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic array for general logic functions
High density
10,000 to 100,000 typical gates (see Table 1)
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
Cost-optimized process
Low cost solution for high-performance communications
applications
System-level features
MultiVolt
TM
I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
Low power consumption
Bidirectional I/O performance (setup time [t
SU
] and clock-to-
output delay [t
CO
]) up to 250 MHz
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Extended temperature range
Table 1. ACEX
TM
1K Device Features
Feature EP1K10 EP1K30 EP1K50 EP1K100
Typical gates 10,000 30,000 50,000 100,000
Maximum system gates 56,000 119,000 199,000 257,000
Logic elements (LEs) 576 1,728 2,880 4,992
EABs 3 6 10 12
Total RAM bits 12,288 24,576 40,960 49,152
Maximum user I/O pins 136 171 249 333
2 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
Operate with a 2.5-V internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLock
TM
and ClockBoost
TM
options for reduced clock delay,
clock skew, and clock multiplication
Built-in, low-skew clock distribution trees
–100% functional testing of all devices; test vectors or scan chains
are not required
Pull-up on I/O pins before and during configuration
Flexible interconnect
–FastTrack
®
Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Powerful I/O pins
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
–Clamp to V
CCIO
user-selectable on a pin-by-pin basis
Supports hot-socketing
Altera Corporation 3
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Software design support and automatic place-and-route provided by
Altera development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Flexible package options are available in 100 to 484 pins, including
the innovative FineLine BGA
TM
packages (see Tables 2 and 3)
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
Notes:
(1) ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine
BGA packages.
(2) Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices.
(3) This option is supported with a 256-pin FineLine BGA package. By using SameFrame
TM
pin migration, all FineLine
BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine
BGA packages.
Table 2. ACEX 1K Package Options & I/O Pin Count Notes (1), (2)
Device 100-Pin TQFP 144-Pin TQFP 208-Pin PQFP 256-Pin
FineLine BGA
484-Pin
FineLine BGA
EP1K10 66 92 120 136 136 (3)
EP1K30 102 147 171 171 (3)
EP1K50 102 147 186 249
EP1K100 147 186 333
Table 3. ACEX 1K Package Sizes
Device 100-Pin TQFP 144-Pin TQFP 208-Pin PQFP 256-Pin
FineLine BGA
484-Pin
FineLine BGA
Pitch (mm) 0.50 0.50 0.50 1.0 1.0
Area (mm
2
) 256 484 936 289 529
Length × width
(mm × mm)
16 × 16 22 × 22 30.6 × 30.6 17 × 17 23 × 23
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