DUAL OUTPUT VOLTAGE DCP AND DCVs
Ripple and Noise
PCB LAYOUT
THERMAL MANAGEMENT
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
Clearly, increasing the capacitance has a much The SYNC
IN
pin, when not being used, is best left as
smaller effect on the output ripple voltage than does a floating pad. A ground ring or annulus connected
reducing the value of the ESR for the filter capacitor. around the pin prevents noise being conducted onto
the pin. If the SYNC
IN
pin is to be connected to one
or more SYNC
IN
pins, then the linking trace should be
narrow and must be kept short in length. In addition,
The voltage output for the dual DCPs is half wave
no other trace should be in close proximity to this
rectified; therefore, the discharge time is 1.25 µ s.
trace because that will increase the stray capacitance
Repeating the above calculations using the 100%
on this pin. In turn, the stray capacitance affects the
load resistance of 25 Ω (0.2A per output), the results
performance of the oscillator.
are:
τ = 25 µ s
t
DIS
= 1.25 µ s
Careful consideration should be given to the layout of
V
DIS
= 244mV
the PCB in order to obtain the best results.
V
ESR
= 20mV
The DCP02 is a switching power supply, and as such
Ripple Voltage = 266mV
can place high peak current demands on the input
supply. In order to avoid the supply falling
This time, it is the capacitor discharging that
momentarily during the fast switching pulses, ground
contributes to the largest component of ripple.
and power planes should be used to connect the
Changing the output filter to 10 µ F, and repeating the
power to the input of DCP02. If this connection is not
calculations, the result is:
possible, then the supplies must be connected in a
Ripple Voltage = 45mV.
star formation with the traces made as wide as
This value is composed of almost equal components.
possible.
The previous calculations are given only as a guide.
If the SYNC
IN
pin is being used, then the trace
Capacitor parameters usually have large tolerances
connection between device SYNC
IN
pins should be
and can be susceptible to environmental conditions.
short to avoid stray capacitance. If the SYNC
IN
pin is
not being used, it is advisable to place a guard ring
(connected to input ground) around this pin to avoid
any noise pick up.
Figure 11 and Figure 12 illustrate a printed circuit
The output should be taken from the device using
board (PCB) layout for the two conventional
ground and power planes, thereby ensuring minimum
(DCP01/02, DCV01), and two SO-28 surface-mount
losses.
packages (DCP02U). Figure 13 shows the schematic.
A good quality, low-ESR ceramic capacitor placed as
Input power and ground planes have been used,
close as practical across the input reduces reflected
providing a low-impedance path for the input power.
ripple and ensures a smooth startup.
For the output, the common or 0V has been
connected via a ground plane, while the connections
A good quality. low-ESR capacitor (ceramic
for the positive and negative voltage outputs are
preferred) placed as close as practical across the
conducted via wide traces in order to minimize
rectifier output terminal and output ground gives the
losses.
best ripple and noise performance. See Application
Bulletin SBVA012, DC-to-DC Converter Noise
The location of the decoupling capacitors in close
Reduction , for more information on noise rejection.
proximity to their respective pins ensures low losses
due to the effects of stray inductance, thus improving
the ripple performance. This location is of particular
importance to the input decoupling capacitor,
Due to the high power density of this device, it is
because this capacitor supplies the transient current
advisable to provide ground planes on the input and
associated with the fast switching waveforms of the
output.
power drive circuits.
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