DS1501/DS1511 Y2K Watchdog Real-Time Clock

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Control B Register (0Fh)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TE CS BME TPE TIE KIE WDE WDS

TE, Transfer Enable Bit (0Fh Bit 7)

When the TE bit is 1, the update transfer functions normally by advancing the counts once per second. When the

TE bit is written to 0, any update transfer is inhibited and the program can initialize the time and calendar bytes

without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. TE is a

read/write bit that is not modified by internal functions of the DS1501/DS1511.

CS, Crystal Select Bit (0Fh Bit 6)

When CS is set to 0, the oscillator is configured for operation with a crystal that has a 6pF specified load

capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the DS1511 module

and should be set to CS = 0.

BME, Burst-Mode Enable Bit (0Fh Bit 5)

The burst-mode enable bit allows the extended user RAM address registers to automatically increment for

consecutive reads and writes. When BME is set to 1, the automatic incrementing is enabled; when BME is set to 0,

the automatic incrementing is disabled.

TPE, Time-of-Day/Date Alarm Power-Enable Bit (0Fh Bit 4)

The wakeup feature is controlled through the TPE bit. When the TDF flag bit is set to 1, if TPE is 1, the

PWR pin is

driven active. Therefore, setting TPE to 1 enables the wakeup feature. Writing a 0 to TPE disables the wakeup

feature.

TIE, Time-of-Day/Date Alarm Interrupt-Enable Bit (0Fh Bit 3)

The TIE bit allows the TDF flag to assert an interrupt. When the TDF flag bit is set to 1, if TIE is 1, the IRQF flag bit

is set to 1. Writing a 0 to the TIE bit prevents the TDF flag from setting the IRQF flag. This bit is automatically

cleared to logic 0 by the internal power-on reset when power is applied and V

rises above the power-fail voltage.

KIE, Kickstart Enable-Interrupt Bit (0Fh Bit 2)

The KIE bit allows the KSF flag to assert an interrupt. When the KSF flag bit is set to 1, if KIE is a 1, the IRQF flag

bit is set to 1. Writing a 0 to the KIE bit prevents the KSF flag from setting the IRQF flag. This bit is automatically

cleared to logic 0 by the internal power-on reset when power is applied and V

rises above the power-fail voltage.

WDE, Watchdog Enable Bit (0Fh Bit 1)

When WDE is set to 1, the watchdog function is enabled, and either the

IRQ or RST pin is pulled active, based on

the state of the WDS and WDF bits. This bit is automatically cleared to logic 0 to by the internal power-on reset

when power is applied and V

rises above the power-fail voltage.

WDS, Watchdog Steering Bit (0Fh Bit 0)

If WDS is 0 when the watchdog flag bit WDF is set to 1, the

IRQ pin is pulled low. If WDS is 1 when WDF is set to

1, the watchdog outputs a negative pulse on the

RST output. The WDE bit resets to 0 immediately after RST goes

active. This bit is automatically cleared to logic 0 to by the internal power-on reset when power is applied and V

rises above the power-fail voltage.

CLOCK OSCILLATOR CONTROL

The clock oscillator can be stopped at any time. To increase the shelf life of a backup lithium-battery source, the

oscillator can be turned off to minimize current drain from the battery. The

EOSC bit is used to control the state of

the oscillator, and must be set to 0 for the oscillator to function.

USING THE WATCHDOG TIMER

The watchdog timer can be used to restart an out-of-control processor. The watchdog timer is user programmable

in 10ms intervals ranging from 0.01 seconds to 99.99 seconds. The user programs the watchdog timer by writing

the timeout value into the two BCD watchdog registers (0Ch and 0Dh). The watchdog reloads and restarts

whenever the watchdog times out. If either watchdog register is nonzero, a timeout sets the WDF bit to 1,

DS1501/DS1511 Y2K Watchdog Real-Time Clock

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regardless of the state of the watchdog enable (WDE) bit, to serve as an indication to the processor that a

watchdog timeout has occurred. The watchdog timer operates in two modes, repetitive and single-shot.

If WDE is 1 and the watchdog steering bit (WDS) is 0, the watchdog is in repetitive mode. When the watchdog

times out, both WDF and IRQF are set.

IRQ goes active and IRQF goes to 1. The watchdog timer is reloaded when

the processor performs a write of the watchdog registers and the timeout period restarts. Reading control A register

clears the

IRQ flag.

If WDE and WDS are 1, the watchdog is in single-shot mode. When the watchdog times out,

RST goes active for a

period of 40ms to 200ms. When

RST goes inactive, WDE resets to 0. Writing a value of 00h to both watchdog

registers disables the watchdog timer. The watchdog function is automatically disabled upon power-up by the

power-on reset setting WDE = 0 and WDS = 0. The watchdog registers are not initialized at power-up and should

be initialized by the user.

Note: The TE bit must be used to disable transfers when writing to the watchdog registers.

The following summarizes the configurations in which the watchdog can be used:

WDE = 0 and WDS = 0: WDF is set.

WDE = 0 and WDS = 1: WDF is set.

WDE = 1 and WDS = 0: WDF and IRQF are set, and the

IRQ pin is pulled low.

WDE = 1 and WDS = 1: WDF is set, the

RST pin pulses low, and WDE resets to 0.

WAKEUP/KICKSTART

The DS1501/DS1511 incorporate a wakeup feature, which powers on at a predetermined day/date and time by

activating the

PWR output pin. Additionally, the kickstart feature allows the system to be powered up in response to

a low-going transition on the

KS pin, without operating voltage applied to the V

pin. As a result, system power

can be applied upon such events as key closure or a modem-ring-detect signal. To use either the wakeup or the

kickstart features, the DS1501DS1511 must have an auxiliary battery connected to the V

BAUX

pin, and the oscillator

must be running.

The wakeup feature is controlled through the time-of-day/date power-enable bit (TPE). Setting TPE to 1 enables

the wakeup feature. Transfers (TE) must be enabled for a wake up event to occur. Writing TPE to 0 disables the

wakeup feature. The kickstart feature is always enabled as long as V

BAUX

is present.

If the wakeup feature is enabled, while the system is powered down (no V

voltage), the clock/calendar monitors

the current day or date for a match condition with day/date alarm register (0Bh). With the day/date alarm register,

the hours, minutes, and seconds alarm bytes in the clock/calendar register map (02h, 01h, and 00h) are also

monitored. As a result, a wakeup occurs at the day or date and time specified by the day/date, hours, minutes, and

seconds alarm register values. This additional alarm occurs regardless of the programming of the TIE bit. When the

match condition occurs, the

PWR pin is automatically driven low. This output can turn on the main system power

supply that provides V

voltage to the DS1501/DS1511, as well as the other major components in the system.

Also at this time, the time-of-day/date alarm flag is set (TDF), indicating a wakeup condition has occurred.

If V

BAUX

is present, while V

is low, the KS input pin is monitored for a low-going transition of minimum pulse width

KSPW

. When such a transition is detected, the PWR line is pulled low, as it is for a wakeup condition. Also at this

time, KSF is set, indicating that a kickstart condition has occurred. The

KS input pin is always enabled and must not

be allowed to float.

The timing associated with the wakeup and kickstarting sequences is illustrated in Figure 7. These functions are

divided into five intervals, labeled 1 to 5 on the diagram.

The occurrence of either a kickstart or wakeup condition causes the

PWR pin to be driven low, as described above.

During Interval 1, if the supply voltage on the V

pin rises above V

before the power-on timeout period (t

POTO

)

expires, then

PWR remains at the active-low level. If V

does not rise above the V

in this time, then the PWR

output pin is turned off and returns to its high-impedance level. In this event, the

IRQ pin also remains tri-stated.

The interrupt flag bit (either TDF or KSF) associated with the attempted power-on sequence remains set until

cleared by software during a subsequent system power-on.

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If V

is applied within the timeout period, the system power-on sequence continues, as shown in Intervals 2 to 5 in

the timing diagram. During Interval 2,

PWR remains active, and IRQ is driven to its active-low level, indicating that

either TDF or KSF was set in initiating the power-on. In the diagram,

KS is assumed to be pulled up to the V

BAUX

supply. Also at this time, the PAB bit is automatically cleared to 0 in response to a successful power-on. The

PWR

line remains active as long as the PAB remains cleared to 0.

At the beginning of Interval 3, the system processor has begun code execution and clears the interrupt condition of

TDF and/or KSF by reading the flags register or by writing TDF and KSF to 0. As long as no other interrupt within

the DS1501/DS1511 is pending, the

IRQ line is taken inactive once these bits are reset, and execution of the

application software can proceed. During this time, the wakeup and kickstart functions can be used to generate

status and interrupts. TDF is set in response to a day/date, hours, minutes, and seconds match condition. KSF is

set in response to a low-going transition on

KS. If the associated interrupt-enable bit is set (TDE and/or KIE), then

the

IRQ line is driven low in response to enabled event. In addition, the other possible interrupt sources within the

DS1501/DS1511 can cause

IRQ to be driven low. While system power is applied, the on-chip logic always attempts

to drive the

PWR pin active in response to the enabled kickstart or wakeup condition. This is true even if PWR was

previously inactive as the result of power being applied by some means other than wakeup or kickstart.

The system can be powered down under software control by setting the PAB bit to 1. The PAB bit can only be set

to 1 after the TDF and KSF flags have been cleared to 0. Setting PAB to 1 causes the open-drain

PWR pin to be

placed in a high-impedance state, as shown at the beginning of Interval 4 in the timing diagram. As V

voltage

decays, the

IRQ output pin is placed in a high-impedance state when V

goes below V

. If the system is to be

again powered on in response to a wakeup or kickstart, then both the TDF and KSF flags should be cleared, and

TPE and/or KIE should be enabled prior to setting the PAB bit.

During Interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM is in effect

and

IRQ is tri-stated, and monitoring of wakeup and kickstart takes place. If PRS = 1, PWR stays active; otherwise,

if PRS = 0,

PWR is tri-stated.

SQUARE-WAVE OUTPUT

The square-wave output is enabled and disabled through the E32K bit. If the square wave is enabled (E32K = 0)

and the oscillator is running, then a 32.768kHz square wave is output on the SQW pin. If the battery-backup

32kHz-enable bit (BB32) is enabled, and voltage is applied to V

BAUX

, then the 32.768kHz square wave is output on

the SQW pin in the absence of V

BATTERY MONITOR

The DS1501/DS1511 constantly monitor the battery voltage of the backup-battery sources (V

BAT

and V

BAUX

). The

battery low flags BLF1 and BLF2 are set to 1 if the battery voltages on V

BAT

and V

BAUX

are less than V

BLF

(typical);

otherwise, BLF1 and BLF2 are 0. BLF1 monitors V

BAT

and BLF2 monitors V

BAUX

256 x 8 EXTENDED RAM

Two on-chip latch registers control access to the SRAM. One register is used to hold the SRAM address; the other

is used to hold read/write data. The SRAM address space is from 00h to FFh. The 8-bit address of the RAM

location to be accessed must be loaded into the extended RAM address register located at 10h. Data in the

addressed location can be read by performing a read operation from location 13h, or written to by performing a

write operation to location 13h. Data in any addressed location can be read or written repeatedly with changing the

address in location 10h.

To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment the

extended RAM address. To enable the burst mode feature, set the BME bit to 1. With burst mode enabled, write

the extended RAM starting address location to register 10h. Then read or write the extended RAM data from/to

OE, CE, or

WE only when register 13h is being accessed (Figure 4). The address pointer wraps around after the last address

is accessed.

Part #	DS1501WEN
Description	Real Time Clock Parallel 256Byte 28-Pin TSOP - Rail/Tube
Category	IC
Availability	Out of Stock
Qty	0

DS1501WEN

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Technical Document