© 2000 Fairchild Semiconductor Corporation DS006400 www.fairchildsemi.com
Revised March 2000
DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register
8-Bit Parallel-In/Serial-Out Shift Register
These parallel-in or serial-in, serial-out shift registers fea-
ture gated clock inputs and an overriding clear input. All
inputs are buffered to lower the drive requirements to one
normalized load, and input clamping diodes minimize
switching transients to simplify system design. The load
mode is established by the shift/load input. When HIGH,
this input enables the serial data input and couples the
eight flip-flops for serial shifting with each clock pulse.
When LOW, the parallel (broadside) data inputs are
enabled and synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the LOW-to-HIGH level edge
of the clock pulse through a two-input NOR gate, permitting
one input to be used as a clock-enable or clock-inhibit func-
tion. Holding either of the clock inputs HIGH inhibits clock-
ing; holding either LOW enables the other clock input. This
allows the system clock to be free running, and the register
can be stopped on command with the other clock input.
The clock-inhibit input should be changed to the high level
only while the clock input is HIGH. A buffered, direct clear
input overrides all other inputs, including the clock, and
sets all flip-flops to zero.
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
DM74LS166M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS166WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS166N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide