Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

DM74LS161AN

Part # DM74LS161AN
Description Counter ICs Syn 4-Bit BinaryCtr
Category IC
Availability In Stock
Qty 320
Qty Price
1 - 67 $0.24663
68 - 134 $0.19730
135 - 201 $0.16278
202 - 268 $0.15127
269 + $0.13482
Manufacturer Available Qty
National Semiconductor Corp
  • Shipping Freelance Stock: 25
    Ships Immediately
National Semiconductor Corp
Date Code: 8900
  • Shipping Freelance Stock: 220
    Ships Immediately
National Semiconductor Corp
Date Code: 9742
  • Shipping Freelance Stock: 10
    Ships Immediately
National Semiconductor Corp
Date Code: 8652
  • Shipping Freelance Stock: 40
    Ships Immediately
National Semiconductor Corp
  • Shipping Freelance Stock: 25
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2000 Fairchild Semiconductor Corporation DS006397 www.fairchildsemi.com
August 1986
Revised April 2000
DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters
DM74LS161A • DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The DM74LS161A and DM74LS163A are 4-bit
binary counters. The carry output is decoded by means of
a NOR gate, thus preventing spikes during the normal
counting mode of operation. Synchronous operation is pro-
vided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so
instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive-going) edge of the
clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the DM74LS161A is asynchro-
nous; and a low level at the clear input sets all four of the
flip-flop outputs LOW, regardless of the levels of clock,
load, or enable inputs. The clear function for the
DM74LS163A is synchronous; and a low level at the clear
inputs sets all four of the flip-flop outputs LOW after the
next clock pulse, regardless of the levels of the enable
inputs. This synchronous clear allows the count length to
be modified easily, as decoding the maximum count
desired can be accomplished with one external NAND
gate. The gate output is connected to the clear input to
synchronously clear the counter to all low outputs.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output.
Both count-enable inputs (P and T) must be HIGH to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-
level output pulse with a duration approximately equal to
the high-level portion of the Q
A
output. This high-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages. HIGH-to-LOW level transitions at the
enable P or T inputs may occur, regardless of the logic
level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, dis-
abled, loading, or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times.
Features
Synchronously programmable
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Typical propagation time, clock to Q output 14 ns
Typical clock frequency 32 MHz
Typical power dissipation 93 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
DM74LS161AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS161AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS163AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS163AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
DM74LS161A • DM74LS163A
Connection Diagram
Logic Diagram
DM74LS163A
The DM74LS161A is similar, however, the clear buffer is connected directly to the flip-flops.
3 www.fairchildsemi.com
DM74LS161A • DM74LS163A
Parameter Measurement Information
Switching Time Waveforms
The input pulses are supplied by generators having the following characteristics:
PRR 1 MHz, duty cycle 50%, Z
OUT
50, t
R
10 ns, t
F
10 ns.
Vary PRR to measure f
MAX
.
Outputs Q
D
and carry are tested at t
N+16
where t
N
is the bit time when all outputs are LOW.
V
REF
= 1.5V.
Switching Time Waveforms
The input pulses are supplied by generators having the following characteristics:
PRR 1 MHz, duty cycle 50%, Z
OUT
50, t
R
6 ns, t
F
6 ns. Vary PRR to measure f
MAX
.
Enable P and enable T setup times are measured at t
N+0
.
V
REF
= 1.3V.
1234NEXT