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DM74LS109AN

Part # DM74LS109AN
Description IC F/F DUAL JK EDGE-TRIG 16-DIP
Category IC
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National Semiconductor Corp
Date Code: 8448
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2000 Fairchild Semiconductor Corporation DS006368 www.fairchildsemi.com
June 1986
Revised March 2000
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
DM74LS109A
Dual Positive-Edge-Triggered J-K
Flip-Flop with
Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K
flip-flops with complementary outputs. The J and
K
data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge
of the clock. The data on the J and K
inputs may be
changed while the clock is HIGH or LOW as long as setup
and hold times are not violated. A low logic level on the
preset or clear inputs will set or reset the outputs regard-
less of the logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
= Rising Edge of Pulse
Q
0
= The output logic level of Q before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each active transition of the clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and/or clear inputs return to their inactive (HIGH) state.
Order Number Package Number Package Description
DM74LS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR CLR CLK J K
QQ
LHXXX H L
HLXXX L H
L L X X X H (Note 1) H (Note 1)
HH LL L H
HH H L Toggle
HH LH Q
0
Q
0
HH HH H L
HH LXX Q
0
Q
0
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DM74LS109A
Absolute Maximum Ratings(Note 2)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 3: C
L
= 15 pF, R
L
= 2 k, T
A
= 25°C and V
CC
= 5V.
Note 4: C
L
= 50 pF, R
L
= 2 k, T
A
= 25°C and V
CC
= 5V.
Note 5: The symbol () indicates the rising edge of the clock pulse is used for reference.
Note 6: T
A
= 25°C and V
CC
= 5V.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current 0.4 mA
I
OL
LOW Level Output Current 8 mA
f
CLK
Clock Frequency (Note 3) 0 25 MHz
f
CLK
Clock Frequency (Note 4) 0 20 MHz
t
W
Pulse Width Clock HIGH 18
(Note 3) Preset LOW 15 ns
Clear LOW 15
t
W
Pulse Width Clock HIGH 25
(Note 4) Preset LOW 20 ns
Clear LOW 20
t
SU
Setup Time Data HIGH 30
ns
(Note 3)(Note 5) Data LOW 20
t
SU
Setup Time Data HIGH 35
ns
(Note 5)(Note 4) Data LOW 25
t
H
Hold Time (Note 6) 0 ns
T
A
Free Air Operating Temperature 0 70 °C
3 www.fairchildsemi.com
DM74LS109A
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 7: All typicals are at V
CC
= 5V, T
A
= 25°C.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V
O
= 2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 9: I
CC
is measured with all outputs OPEN, with CLOCK grounded after setting the Q and Q outputs HIGH in turn.
Switching Characteristics
at V
CC
= 5V and T
A
= 25°C
Symbol Parameter Conditions Min
Typ
Max Units
(Note 7)
V
I
Input Clamp Voltage V
CC
= Min, I
I
= 18 mA 1.5 V
V
OH
HIGH Level V
CC
= Min, I
OH
= Max
2.7 3.4 V
Output Voltage V
IL
= Max, V
IH
= Min
V
OL
LOW Level V
CC
= Min, I
OL
= Max
0.35 0.5
Output Voltage V
IL
= Max, V
IH
= Min V
I
OL
= 4 mA, V
CC
= Min 0.25 0.4
I
I
Input Current @ Max V
CC
= Max J, K 0.1
Input Voltage V
I
= 7V Clock 0.1
mA
Preset 0.2
Clear 0.2
I
IH
HIGH Level V
CC
= Max J,K 20
Input Current V
I
= 2.7V Clock 20
µA
Preset 40
Clear 40
I
IL
LOW Level V
CC
= Max J, K 0.4
Input Current V
I
= 0.4V Clock 0.4
mA
Preset 0.8
Clear 0.8
I
OS
Short Circuit Output Current V
CC
= Max (Note 8) 20 100 mA
I
CC
Supply Current V
CC
= Max (Note 9) 4 8 mA
From (Input)
R
L
= 2 k
Symbol Parameter
To (Output)
C
L
= 15 pF C
L
= 50 pF Units
MinMaxMinMax
f
MAX
Maximum Clock Frequency 25 20 MHz
t
PLH
Propagation Delay Time Clock to
25 35 ns
LOW-to-HIGH Level Output Q or Q
t
PHL
Propagation Delay Time Clock to
30 35 ns
HIGH-to-LOW Level Output Q or Q
t
PLH
Propagation Delay Time Clear
25 35 ns
LOW-to-HIGH Level Output to Q
t
PHL
Propagation Delay Time Clear
30 35 ns
HIGH-to-LOW Level Output to Q
t
PLH
Propagation Delay Time Preset
25 35 ns
LOW-to-HIGH Level Output to Q
t
PHL
Propagation Delay Time Preset
30 35 ns
HIGH-to-LOW Level Output to Q
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