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DM74ALS541N

Part # DM74ALS541N
Description IC BUFF/DVR TRI-ST 8BIT 20DIP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2000 Fairchild Semiconductor Corporation DS009171 www.fairchildsemi.com
October 1986
Revised February 2000
DM74ALS541 Octal Buffer and Line Driver with 3-STATE Outputs
DM74ALS541
Octal Buffer and Line Driver with 3-STATE Outputs
General Description
This octal buffer and line driver is designed to have the per-
formance of the DM74ALS240A series and, at the same
time, offer a pinout with inputs and outputs on opposite
sides of the package. This arrangement greatly enhances
circuit board layout. The 3-STATE control gate is a 2-input
NOR such that if either G1 or G2 is HIGH, all eight outputs
are in the high impedance state.
Features
Advanced oxide-isolated ion-implanted Schottky TTL
process
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
Data flow-thru pinout (all inputs on opposite side from
outputs)
P-N-P Inputs reduce DC loading
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Don't Care (Either LOW or HIGH Logic Level)
Hi-Z = High Impedance (OFF) State
Order Number Package Number Package Description
DM74ALS541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Input Output
G
1G2A Y
H X X Hi-Z
X H X Hi-Z
LLLL
LLHH
www.fairchildsemi.com 2
DM74ALS541
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended free air temperature range
Supply Voltage 7V
Input Voltage: Control Inputs 7V
Voltage Applied to a Disabled
3-STATE Output 5.5V
Operating Free-Air Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Typical θ
JA
N Package 58.5°C/W
M Package 77.5°C/W
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current 15 mA
I
OL
LOW Level Output Current 24 mA
T
A
Free Air Operating Temperature 0 70 °C
Symbol Parameter Test Conditions Min Typ Max Units
V
IK
Input Clamp Voltage V
CC
= Min, I
I
= 18 mA 1.2 V
V
OH
HIGH Level V
CC
= 4.5V to 5.5V I
OH
= 0.4 mA V
CC
2
Output Voltage V
CC
= Min I
OH
= 3 mA 2.4 3.2 V
I
OH
= Max 2
V
OL
LOW Level V
CC
= Min I
OL
= 12 mA 0.25 0.4
mA
Output Voltage I
OL
= 24 mA 0.35 0.5
I
I
Input Current at Maximum
V
CC
= Max, V
I
= 7V 100 µA
Input Voltage
I
IH
HIGH Level Input Current V
CC
= Max, V
I
= 2.7V 20 µA
I
IL
LOW Level Input Current V
CC
= Max, V
I
= 0.4V 100 µA
I
OZH
HIGH Level 3-STATE
V
CC
= Max, V
O
= 2.7V 20 µA
Output Current
I
OZL
LOW Level 3-STATE
V
CC
= Max, V
O
= 0.4V 20 µA
Output Current
I
O
Output Drive Current V
CC
= Max, V
O
= 2.25V 30 112 mA
I
CC
Supply Current V
CC
= Max Outputs HIGH 6 14
Outputs LOW 15 25 mA
Outputs Disabled 13.5 22
3 www.fairchildsemi.com
DM74ALS541
Switching Characteristics
over recommended operating free air temperature range
Symbol Parameter Conditions
From (Input)
Min Max Units
To (Output)
t
PLH
Propagation Delay Time V
CC
= 4.5V to 5.5V,
A to Y 4 14 ns
LOW-to-HIGH Level Output R
1
= R
2
= 500,
t
PHL
Propagation Delay Time C
L
= 50 pF
A to Y 2 10 ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time
G to Y 5 15 ns
to HIGH Level Output
t
PZL
Output Enable Time
G to Y 8 20 ns
to LOW Level Output
t
PHZ
Output Disable Time
G to Y 1 10 ns
from HIGH Level Output
t
PLZ
Output Disable Time
G to Y 2 12 ns
from LOW Level Output
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