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DM74ALS165MX

Part # DM74ALS165MX
Description IC SHIFT REGISTER 8BIT 16SOIC
Category IC
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Fairchild Semiconductor
Date Code: 9912
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2000 Fairchild Semiconductor Corporation DS006712 www.fairchildsemi.com
January 1986
Revised February 2000
DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, Q
H
. Parallel-in
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, Q
H
.
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD
is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD
is held HIGH. The parallel inputs to
the register are enabled while SH/LD
is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Features
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Level (steady-state),
L = LOW Level (steady-state)
X = Don't Care (any input, including transitions)
= Transition from LOW-to-HIGH level
a...h = The level of steady-state input at inputs A through H, respectively
Q
A0
, Q
B0
, Q
H0
= The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established
Q
An
, Q
Gn
= The level of Q
A
or Q
G
, respectively, before the most recent
transition of the clock
Order Number Package Number Package Description
DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Internal
Shift/ Clock Clock Serial Parallel Outputs Output
Load Inhibit
A...H Q
A
Q
B
Q
H
L X X X a...h a b h
HL LX XQ
A0
Q
B0
Q
H0
HL HXHQ
An
Q
Gn
HL LXLQ
An
Q
Gn
H LH XHQ
An
Q
Gn
H LL XLQ
An
Q
Gn
HH XX XQ
A0
Q
B0
Q
H0
www.fairchildsemi.com 2
DM74ALS165
Logic Diagram
Timing Diagram
Typical Shift, Load, and Inhibit Sequences
3 www.fairchildsemi.com
DM74ALS165
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typical values are at V
CC
= 5V, T
A
= 25°C.
Note 3: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS
.
Note 4: With the outputs open, CLK INH and CLK at 4.5V, and a clock pulse applied to the SH/LD
input, I
CC
is measured first with the parallel inputs at 4.5V,
then with the parallel inputs grounded.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Typical θ
JA
N Package 74.0°C/W
M Package 104.0°C/W
Symbol Parameter Min Typ Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current 0.4 mA
I
OL
LOW Level Output Current 8 mA
f
CLOCK
Clock Frequency 45 MHz
t
W
Pulse Duration CLK HIGH 11
CLK LOW 11 ns
Load 12
t
SU
Setup Time SH/LD 10
ns
Data 10
t
SU
Setup Time CLK INH before CLK 11
ns
Serial before CLK 10
t
H
Hold Time 4 ns
T
A
Operating Free Air Temperature 0 70 °C
Symbol Parameter Conditions Min
Typ
(Note 2)
Max Units
V
IK
Input Clamp Voltage V
CC
= 4.5V, I
I
= 18 mA 1.5 V
V
OH
HIGH Level I
OH
= 0.4 mA
V
CC
2V
Output Voltage V
CC
= 4.5V to 5.5V
V
OL
LOW Level V
CC
= 4.5V I
OL
= 4 mA 0.25 0.4
V
Output Voltage I
OL
= 8 mA 0.35 0.5
I
I
Input Current at Max Input Voltage V
CC
= 5.5V, V
I
= 7V 0.1 mA
I
IH
HIGH Level Input Current V
CC
= 5.5V, V
I
= 2.7V 20 µA
I
IL
LOW Level Input Current V
CC
= 5.5V, V
I
= 0.4V 0.1 mA
I
O
(Note 3) Output Drive Current V
CC
= 5.5V, V
O
= 2.25V 30 112 mA
I
CC
Supply Current V
CC
= 5.5V (Note 4) 16 24 mA
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