© 2000 Fairchild Semiconductor Corporation DS006712 www.fairchildsemi.com
January 1986
Revised February 2000
DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, Q
H
. Parallel-in
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, Q
H
.
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD
is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD
is held HIGH. The parallel inputs to
the register are enabled while SH/LD
is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Features
■ Complementary outputs
■ Direct overriding load (data) inputs
■ Gated clock inputs
■ Parallel-to-serial data conversion
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Level (steady-state),
L = LOW Level (steady-state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a...h = The level of steady-state input at inputs A through H, respectively
Q
A0
, Q
B0
, Q
H0
= The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established
Q
An
, Q
Gn
= The level of Q
A
or Q
G
, respectively, before the most recent
↑ transition of the clock
Order Number Package Number Package Description
DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Internal
Shift/ Clock Clock Serial Parallel Outputs Output
Load Inhibit
A...H Q
A
Q
B
Q
H
L X X X a...h a b h
HL LX XQ
A0
Q
B0
Q
H0
HL ↑ HXHQ
An
Q
Gn
HL ↑ LXLQ
An
Q
Gn
H ↑ LH XHQ
An
Q
Gn
H ↑ LL XLQ
An
Q
Gn
HH XX XQ
A0
Q
B0
Q
H0
