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DM74ALS109AN

Part # DM74ALS109AN
Description IC JK TYPE POS TRG DUAL 16DIP
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $0.11776
Manufacturer Available Qty
National Semiconductor Corp
Date Code: 8712
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2000 Fairchild Semiconductor Corporation DS006196 www.fairchildsemi.com
April 1984
Revised February 2000
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS109A
Dual J-K
Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K
, clock, clear and preset inputs,
and also complementary Q and Q
outputs.
Information at input J or K
is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the J, K
input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K
design allows operation as a D flip-flop by tying the
J and K
inputs together.
Features
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
CC
range
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
Improved AC performance over LS109 at approximately
half the power
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
L = LOW State
H = HIGH State
X = Don't Care
= Positive Edge Transition,
Q
0
= Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when present and
clear inputs return to their inactive (HIGH) level. The output levels in this
condition are not guaranteed to meet the V
OH
specification.
Order Number Package Number Package Description
DM74ALS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR
CLR CK J K QQ
LHXXX H L
HLXXX L H
L L X X X H (Note 1) H (Note 1)
HH LL L H
HH H L TOGGLE
HH LH Q
0
Q
0
HH HH H L
HHLXX Q
0
Q
0
www.fairchildsemi.com 2
DM74ALS109A
Logic Diagram
3 www.fairchildsemi.com
DM74ALS109A
Absolute Maximum Ratings(Note 2)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 3: The () arrow indicates the positive edge of the Clock is used for reference.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Typical θ
JA
N Package 82.5°C/W
M Package 111.5°C/W
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current 0.4 mA
I
OL
LOW Level Output Current 8 mA
f
CLK
Clock Frequency 0 34 MHz
t
W(CLK)
Pulse Width Clock HIGH 14.5 ns
Clock LOW 14.5 ns
t
W
Pulse Width (Note 3) Preset and Clear 15 ns
t
SU
Data Setup Time J or K 15 ns
(Note 3)
PRE
or CLR inactive 10
t
H
Data Hold Time 0 ns
T
A
Free Air Operating Temperature 0 70 °C
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