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DM7476N

Part # DM7476N
Description IC JK TYPE POS TRG DUAL 16DIP
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $3.96198
Manufacturer Available Qty
National Semiconductor Corp
Date Code: 8942
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2000 Fairchild Semiconductor Corporation DS006528 www.fairchildsemi.com
September 1986
Revised February 2000
DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7476
Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs
must not be allowed to change while the clock is HIGH.
The data is transferred to the outputs on the falling edge of
the clock pulse. A LOW logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Ordering Code:
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
= Positive pulse data. The J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q
0
= The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each complete active HIGH level clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (HIGH) level.
Order Number Package Number Package Description
DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR CLR CLK J K Q Q
LHXXX H L
HLXXX L H
LLXXX H
(Note 1)
H
(Note 1)
HH
LLQ
0
Q
0
HH HL H L
HH
LH L H
HH
H H Toggle
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DM7476
Absolute Maximum Ratings(Note 2)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 3: T
A
= 25°C and V
CC
= 5V.
Note 4: The symbol (, ) indicates the edge of the clock pulse is used for reference () for rising edge, () for falling edge.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5: All typicals are at V
CC
= 5V, T
A
= 25°C.
Note 6: Clear is measured with preset HIGH and preset is measured with clear HIGH.
Note 7: Not more than one output should be shorted at a time.
Note 8: With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock input is grounded.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current 0.4 mA
I
OL
LOW Level Output Current 16 mA
f
CLK
Clock Frequency (Note 3) 0 15 MHz
t
W
Pulse Width Clock HIGH 20
(Note 3) Clock LOW 47
ns
Preset LOW 25
Clear LOW 25
t
SU
Input Setup Time (Note 3)(Note 4) 0 ns
t
H
Input Hold Time (Note 3)(Note 4) 0 ns
T
A
Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min
Typ
Max Units
(Note 5)
V
I
Input Clamp Voltage V
CC
= Min, I
I
= 12 mA 1.5 V
V
OH
HIGH Level V
CC
= Min, I
OH
= Max
2.4 3.4 V
Output Voltage V
IL
= Max, V
IH
= Min
V
OL
LOW Level V
CC
= Min, I
OL
= Max
0.2 0.4 V
Output Voltage V
IH
= Min, V
IL
= Max
I
I
Input Current @ Max Input Voltage V
CC
= Max, V
I
= 5.5V 1 mA
I
IH
HIGH Level V
CC
= Max J, K 40
Input Current V
I
= 2.4V Clock 80
µA
Clear 80
Preset 80
I
IL
LOW Level V
CC
= Max J, K 1.6
Input Current V
I
= 0.4V Clock 3.2
mA
(Note 6) Clear 3.2
Preset 3.2
I
OS
Short Circuit Output Current V
CC
= Max (Note 7) 18 55 mA
I
CC
Supply Current V
CC
= Max (Note 8) 18 34 mA
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DM7476
Switching Characteristics
at V
CC
= 5V and T
A
= 25°C
Symbol Parameter
From (Input)
R
L
= 400, C
L
= 15 pF
Units
To (Output) Min Max
f
MAX
Maximum Clock Frequency 15 MHz
t
PHL
Propagation Delay Time
Preset to Q 40 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Preset to Q 25 ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clear to Q 40 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clear to Q 25 ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Q or Q 40 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clock to Q or Q 25 ns
LOW-to-HIGH Level Output
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