DG417/DG418/DG419
Improved, SPST/SPDT Analog Switches
_______________________________________________________________________________________ 7
_____________________________________________________Test Circuits/Timing Diagrams
t
R
< 20ns
t
F
< 20ns
50%
0V
LOGIC
INPUT
V-
-15V
R
L
300Ω
S
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
D (
R
L
)
R
L
+ R
DS(ON
)
SWITCH
INPUT
IN
+3V
t
OFF
0V
D
SWITCH
OUTPUT
0.9 x V
OUT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
VL
V+
C
L
35pF
+5V
+15V
V
OUT
DG417
DG418
t
R
< 20ns
t
F
< 20ns
50%
0V
LOGIC
INPUT
V-
-15V
R
L
1000Ω
D
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
LOGIC
INPUT
S1
IN
t
TRANS
+3V
t
TRANS
V
OUT1
V+
S2
V
OUT
0.8 x V
OUT1
V
OUT2
0.8 x V
OUT2
SWITCH
OUTPUT
VL
DG419
+15V
+5V
C
L
35pF
Figure 2. DG417/DG418 Switching Time
Figure 3. DG419 Transition Time
