Altera Corporation 1–1
February 2005
1. Introduction to the
Stratix GX Device Data Sheet
Overview
The Stratix
®
GX family of devices is Altera’s second FPGA family to
combine high-speed serial transceivers with a scalable, high-performance
logic array. Stratix GX devices include 4 to 20 high-speed transceiver
channels, each incorporating clock data recovery (CDR) technology and
embedded SERDES capability at data rates of up to 3.1875 gigabits per
second (Gbps). These transceivers are grouped by four-channel
transceiver blocks, and are designed for low power consumption and
small die size. The Stratix GX FPGA technology is built upon the Stratix
architecture, and offers a 1.5-V logic array with unmatched performance,
flexibility, and time-to-market capabilities. This scalable,
high-performance architecture makes Stratix GX devices ideal for
high-speed backplane interface, chip-to-chip, and communications
protocol-bridging applications.
Features
■ Transceiver block features are as follows:
● High-speed serial transceiver channels with CDR provides
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
● Devices are available with 4, 8, 16, or 20 high-speed serial
transceiver channels providing up to 127.5 Gbps of full-duplex
serial bandwidth
● Support for transceiver-based protocols, including 10 Gigabit
Ethernet attachment unit interface (XAUI), Gigabit Ethernet
(GigE), and SONET/SDH
● Compatible with PCI Express, SMPTE 292M, Fibre Channel, and
Serial RapidIO I/O standards
● Programmable differential output voltage (V
OD
), pre-emphasis,
and equalization settings for improved signal integrity
● Individual transmitter and receiver channel power-down
capability implemented automatically by the Quartus
®
II
software for reduced power consumption during non-operation
● Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, and 20-bit wide data paths
● 1.5-V pseudo current mode logic (PCML) for 500 Mbps to
3.1875 Gbps
● Support for LVDS, LVPECL, and 3.3-V PCML on reference
clocks and receiver input pins (AC-coupled)
● Built-in self test (BIST)
● Hot insertion/removal protection circuitry
SGX51001-1.0
