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DAC7725N

Part # DAC7725N
Description D/A CONV, QUAD PARALLEL 12-BIT +/-10V - Rail/Tube
Category IC
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Burr-Brown Corporation
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

12-Bit Quad Voltage Output
DIGITAL-TO-ANALOG CONVERTER
®
DAC7724
DAC7725
DESCRIPTION
The DAC7724 and DAC7725 are 12-bit quad voltage
output digital-to-analog converters with guaranteed
12-bit monotonic performance over the specified tem-
perature range. They accept 12-bit parallel input data,
have double-buffered DAC input logic (allowing simul-
taneous update of all DACs), and provide a readback
mode of the internal input registers. An asynchronous
reset clears all registers to a mid-scale code of 800
H
(DAC7724) or to a zero-scale of 000
H
(DAC7725). The
DAC7724 and DAC7725 can operate from a single
+15V supply, or from +15V and –15V supplies.
Low power and small size per DAC make the DAC7724
and DAC7725 ideal for automatic test equipment,
DAC-per-pin programmers, data acquisition systems,
and closed-loop servo-control. The DAC7724 and
DAC7725 are available in a PLCC-28 or a SO-28
package, and offer guaranteed specifications over the
–40°C to +85°C temperature range.
FEATURES
LOW POWER: 250mW max
SINGLE SUPPLY OUTPUT RANGE: +10V
DUAL SUPPLY OUTPUT RANGE: ±10V
SETTLING TIME: 10µs to 0.012%
12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
RESET TO MID-SCALE (DAC7724) OR
ZERO-SCALE (DAC7725)
DATA READBACK
DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
PROCESS CONTROL
CLOSED-LOOP SERVO-CONTROL
MOTOR CONTROL
DATA ACQUISITION SYSTEMS
© 1999 Burr-Brown Corporation PDS-1517B Printed in U.S.A. April, 2000
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
DAC A
DAC
Register A
Input
Register A
I/O
Buffer
Control
Logic
DAC B
DAC
Register B
Input
Register B
DAC C
DAC
Register C
Input
Register C
DAC D
DAC
Register D
Input
Register D
V
REFH
V
CC
V
DD
V
SS
V
OUTD
V
OUTC
V
OUTB
V
OUTA
V
REFL
RESET LDAC
GND
A0
A1
R/W
CS
DB0-DB11
12
For most current data sheet and other product
information, visit www.burr-brown.com
DAC7724
DAC7725
SBAS112
2
®
DAC7724, 7725
SPECIFICATION (DUAL SUPPLY)
At T
A
= –40°C to +85°C, V
CC
= +15V, V
DD
= +5V, V
SS
= –15V, V
REFH
= +10V, V
REFL
= –10V, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC7724N, U DAC7724NB, UB
DAC7725N, U DAC7725NB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error ±2 ±1 LSB
(1)
Linearity Matching
(2)
±2 ±1 LSB
Differential Linearity Error ±1 ±1 LSB
Monotonicity T
MIN
to T
MAX
12 Bits
Zero-Scale Error Code = 000
H
±2 LSB
Zero-Scale Drift 1 ppm/°C
Zero-Scale Matching
(2)
±2 ±1 LSB
Full-Scale Error Code = FFF
H
±2 LSB
Full-Scale Matching
(2)
±2 ±1 LSB
Power Supply Sensitivity At Full Scale 10 ppm/V
ANALOG OUTPUT
Voltage Output
(3)
V
REFL
V
REFH
✻✻V
Output Current ±5 ✻✻mA
Load Capacitance No Oscillation 500 pF
Short-Circuit Current ±20 mA
Short-Circuit Duration To V
SS
, V
CC
, or GND Indefinite
REFERENCE INPUT
V
REFH
Input Range
V
REFL
+1.25
+10 ✻✻V
V
REFL
Input Range –10
V
REFH
– 1.25
✻✻V
Ref High Input Current –0.5 3.0 ✻✻mA
Ref Low Input Current –3.5 0 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time To ±0.012%, 20V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk
Full-Scale Step
0.25 LSB
Digital Feedthrough 2 nV-s
Output Noise Voltage f = 10kHz 65 nV/Hz
DIGITAL INPUT/OUTPUT
Logic Family TTL-Compatible CMOS
Logic Levels
V
IH
I
IH
±10µA 2.4 V
DD
+0.3 ✻✻V
V
IL
I
IL
±10µA –0.3 0.8 ✻✻V
V
OH
I
OH
= –0.8mA 3.6 V
DD
✻✻V
V
OL
I
OL
= 1.6mA 0.0 0.4 ✻✻V
Data Format Straight Binary
POWER SUPPLY REQUIREMENTS
V
DD
+4.75 +5.25 ✻✻V
V
CC
+14.25 +15.75 ✻✻V
V
SS
–14.25 –15.75 ✻✻V
I
DD
50 ✻✻ µA
I
CC
6 8.5 ✻✻ mA
I
SS
–8 –6 ✻✻ mA
Power Dissipation 180 250 ✻✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
NOTES: (1) LSB means Least Significant Bit, when V
REFH
equals +10V and V
REFL
equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within
the specified error band. (3) Ideal output voltage, does not take into account zero or full-scale error.
3
®
DAC7724, 7725
SPECIFICATION (SINGLE SUPPLY)
At T
A
= –40°C to +85°C, V
CC
= +15V, V
DD
= +5V, V
SS
= GND, V
REFH
= +10V, V
REFL
= 0V, unless otherwise noted.
DAC7724N, U DAC7724NB, UB
DAC7725N, U DAC7725NB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error
(1)
±2 ±1 LSB
(2)
Linearity Matching
(3)
±2 ±1 LSB
Differential Linearity Error ±1 ±1 LSB
Monotonicity T
MIN
to T
MAX
12 Bits
Zero-Scale Error Code = 004
H
±4 LSB
Zero-Scale Drift 2 ppm/°C
Zero-Scale Matching
(3)
±4 ±2 LSB
Full-Scale Error Code = FFF
H
±4 LSB
Full-Scale Matching
(3)
±4 ±2 LSB
Power Supply Sensitivity At Full Scale 20 ppm/V
ANALOG OUTPUT
Voltage Output
(4)
V
REFL
V
REFH
✻✻V
Output Current ±5 mA
Load Capacitance No Oscillation 500 pF
Short-Circuit Current ±20 mA
Short-Circuit Duration To V
CC
or GND Indefinite
REFERENCE INPUT
V
REFH
Input Range
V
REFL
+1.25
+10 ✻✻V
V
REFL
Input Range 0
V
REFH
– 1.25
✻✻V
Ref High Input Current –0.3 1.5 ✻✻mA
Ref Low Input Current –2.0 0 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time
(5)
To ±0.012%, 10V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk 0.25 LSB
Digital Feedthrough 2 nV-s
Output Noise Voltage f = 10kHz 65 nV/Hz
DIGITAL INPUT/OUTPUT
Logic Family TTL-Compatible CMOS
Logic Levels
V
IH
I
IH
±10µA 2.4 V
DD
+0.3 ✻✻V
V
IL
I
IL
±10µA –0.3 0.8 ✻✻V
V
OH
I
OH
= –0.8mA 3.6 V
DD
✻✻V
V
OL
I
OL
= 1.6mA 0.0 0.4 ✻✻V
Data Format Straight Binary
POWER SUPPLY REQUIREMENTS
V
DD
+4.75 +5.25 ✻✻V
V
CC
14.25 15.75 ✻✻V
I
DD
50 ✻✻ µA
I
CC
3.0 ✻✻ mA
Power Dissipation 45 mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
NOTES: (1) If V
SS
= 0V, specification applies at code 004
H
and above. (2) LSB means Least Significant Bit, when V
REFH
equals +10V and V
REFL
equals 0V, then
one LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFF
H
to 004
H
.
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