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CY7C68013A-128AXC

Part # CY7C68013A-128AXC
Description MCU 8BIT CISC ROMLESS 3.3V 128TQFP - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

EZ-USB FX2LP™ USB Microcontroller
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-08032 Rev. *G Revised February 1, 2005
1.0 Features (CY7C68013A/14A/15A/16A)
USB 2.0–USB-IF high speed certified (TID # 40440111)
Single-chip integrated USB 2.0 transceiver, smart SIE,
and enhanced 8051 microprocessor
Fit, form and function compatible with the FX2
Pin-compatible
Object-code-compatible
Functionally-compatible (FX2LP is a superset)
Ultra Low power: I
CC
no more than 85 mA in any mode
Ideal for bus and battery powered applications
Software: 8051 code runs from:
Internal RAM, which is downloaded via USB
Internal RAM, which is loaded from EEPROM
External memory device (128 pin package)
16 KBytes of on-chip Code/Data RAM
Four programmable BULK/INTERRUPT/ISOCHRO-
NOUS endpoints
Buffering options: double, triple, and quad
Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
8- or 16-bit external data interface
Smart Media Standard ECC generation
GPIF (General Programmable Interface)
Allows direct connection to most parallel interface
Programmable waveform descriptors and configu-
ration registers to define waveforms
Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
Integrated, industry-standard enhanced 8051
48-MHz, 24-MHz, or 12-MHz CPU operation
Four clocks per instruction cycle
Two USARTS
Three counter/timers
Expanded interrupt system
Two data pointers
3.3V operation with 5V tolerant inputs
Vectored USB interrupts and GPIF/FIFO interrupts
Separate data buffers for the Set-up and Data portions
of a CONTROL transfer
Integrated I
2
C controller, runs at 100 or 400 kHz
Four integrated FIFOs
Integrated glue logic and FIFOs lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
Uses external clock or asynchronous strobes
Easy interface to ASIC and DSP ICs
1.1 Features (CY7C68013A/14A only)
CY7C68014A: Ideal for battery powered applications
Suspend current: 100 µA (typ)
CY7C68013A: Ideal for non-battery powered applica-
tions
Suspend current: 300 µA (typ)
Available in four lead-free packages with up to 40 GPIOs
128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),
56-pin QFN (24 GPIOs) and 56-pin SSOP (24 GPIOs)
Address (16)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
VCC
1.5k
D+
D–
Address (16) / Data Bus (8)
FX2LP
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full- and high-speed
XCVR
Additional I/Os (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes/s
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Abundant I/O
including two USARTS
High-performance micro
using standard tools
with lower-power options
Master
Figure 1-1. Block Diagram
connected for
full speed
ECC
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G Page 2 of 55
1.2 Features (CY7C68015A/16A only)
CY7C68016A: Ideal for battery powered applications
Suspend current: 100 µA (typ)
CY7C68015A: Ideal for non-battery powered applica-
tions
Suspend current: 300 µA (typ)
Available in lead-free 56-pin QFN package (26 GPIOs)
2 more GPIOs than CY7C68013A/14A enabling addi-
tional features in same footprint
Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB
FX2LP (CY7C68013A/14A) is a low-power version of the
EZ-USB FX2 (CY7C68013), which is a highly integrated,
low-power USB 2.0 microcontroller. By integrating the USB 2.0
transceiver, serial interface engine (SIE), enhanced 8051
microcontroller, and a programmable peripheral interface in a
single chip, Cypress has created a very cost-effective solution
that provides superior time-to-market advantages with low
power to enable bus powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second, the maximum-allowable
USB 2.0 bandwidth, while still using a low-cost 8051 microcon-
troller in a package as small as a 56 QFN. Because it incorpo-
rates the USB 2.0 transceiver, the FX2LP is more economical,
providing a smaller footprint solution than USB 2.0 SIE or
external transceiver implementations. With EZ-USB FX2LP,
the Cypress Smart SIE handles most of the USB 1.1 and 2.0
protocol in hardware, freeing the embedded microcontroller for
application-specific functions and decreasing development
time to ensure USB compatibility.
The General Programmable Interface (GPIF) and
Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides
an easy and glueless interface to popular interfaces such as
ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.
The FX2LP draws considerably less current than the FX2
(CY7C68013), has double the on-chip code/data RAM and is
fit, form and function compatible with the 56-, 100-, and 128-
pin FX2.
Four packages are defined for the family: 56 SSOP, 56 QFN,
100 TQFP, and 128 TQFP.
2.0 Applications
Portable video recorder
MPEG/TV conversion
DSL modems
•ATA interface
Memory card readers
Legacy conversion devices
Cameras
Scanners
Home PNA
Wireless LAN
MP3 players
•Networking
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G Page 3 of 55
3.0 Functional Overview
3.1 USB Signaling Speed
FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbps
High speed, with a signaling bit rate of 480 Mbps.
FX2LP does not support the low-speed signaling mode of
1.5 Mbps.
3.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system,
three timer/counters, and two USARTs.
3.2.1 8051 Clock Frequency
FX2LP has an on-chip oscillator circuit that uses an external
24-MHz (±100-ppm) crystal with the following characteristics:
Parallel resonant
Fundamental mode
•500-µW drive level
12-pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to
480 MHz, as required by the transceiver/PHY, and internal
counters divide it down for use as the 8051 clock. The default
8051 clock frequency is 12 MHz. The clock frequency of the
8051 can be changed by the 8051 through the CPUCS
register, dynamically.
The CLKOUT pin, which can be three-stated and inverted
using internal control bits, outputs the 50% duty cycle 8051
clock, at the selected 8051 clock frequency—48, 24, or 12
MHz.
3.2.2 USARTS
FX2LP contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface
pins are available on separate I/O pins, and are not multi-
plexed with port pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230-KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The
internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)
such that it always presents the correct frequency for 230-
KBaud operation.
[1]
3.2.3 Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in Table 3-1. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with0
and “8” contain bit-addressable registers. The four I/O ports
A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in FX2LP. Because of
the faster and more efficient SFR addressing, the FX2LP I/O
ports are not addressable in external RAM space (using the
MOVX instruction).
3.3 I
2
C Bus
FX2LP supports the I
2
C bus as a master only at 100-/400-KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I
2
C
device is connected.
3.4 Buses
All packages: 8- or 16-bit FIFO” bidirectional data bus, multi-
plexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
Figure 3-1. Crystal Configuration
12 pf
12 pf
24 MHz
20 × PLL
C1
C2
12-pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
Note:
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.
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