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CY7B923-JI

Part # CY7B923-JI
Description PHY 1TX-CH 160Mbps/330Mbps 28-Pin PLCC - Rail/Tube
Category IC
Availability In Stock
Qty 3
Qty Price
1 - 2 $35.93734
3 + $27.22526
Manufacturer Available Qty
CYPRESS SEMICONDUCTOR
Date Code: 9920
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

HOTLink™ Transmitter/Receiver
CY7B923
CY7B933
Cypress Semiconductor Corporation
3901 North First Street San Jose CA 95134 408-943-2600
April 5
,
1999
Features
Fibre Channel compliant
IBM ESCON
®
compliant
DVB-ASI compliant
ATM compliant
8B/10B-coded or 10-bit unencoded
Standard HOTLink: 160–330 Mbps
High Speed HOTLink: 160–400 Mbps for high speed ap-
plications
Low Speed HOTLink: 150–160 Mbps for Low Cost Fiber
applications
TTL synchronous I/O
No external PLL components
Triple PECL 100K serial outputs
Dual PECL 100K serial inputs
Low power: 350 mW (Tx), 650 mW (Rx)
Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
Built-In Self-Test
Single +5V supply
28-pin SOIC/PLCC/LCC
0.8
µ
BiCMOS
Functional Description
The CY7B923 HOTLink™ Transmitter and CY7B933 HOTLink
Receiver are point-to-point communications building blocks
that transfer data over high-speed serial links (fiber, coax, and
twisted pair). Standard HOTLink data rates range from
160-330 Mbits/second. Higher speed HOTLink is also avail-
able for high speed applications (160-400 Mbits/second), as
well as for those Low Cost applications HOTLink-155 (150-160
Mbits/second operations).
Figure 1
illustrates typical connec-
tions to host systems or controllers.
Eight bits of user data or protocol information are loaded into
the HOTLink transmitter and are encoded. Serial data is shift-
ed out of the three differential positive ECL (PECL) serial ports
at the bit rate (which is 10 times the byte rate).
The HOTLink receiver accepts the serial bit stream at its dif-
ferential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information nec-
essary for data reconstruction. The bit stream is deserialized,
decoded, and checked for transmission errors. Recovered
bytes are presented in parallel to the receiving host along with
a byte-rate clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. I/O signals
are available to create a seamless interface with both asyn-
chronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern generator and checker
allows testing of the transmitter, receiver, and the connecting
link as a part of a system diagnostic check.
HOTLink devices are ideal for a variety of applications where
a parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
workstations, servers, mass storage, and video transmission
equipment.
HOTLink is a trademark of cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
CY7B923 Transmitter Logic Block Diagram
B923–1
INPUT REGISTER
D
0
7
(D
b
h
)
SC/D(D
a
)
SVS(D
j
)
ENABLE
ENCODER
SHIFTER
OUTA
OUTB
OUTC
FOTO
CKW
CLOCK
GENERATOR
ENAENNRP
TEST
LOGIC
MODE
BISTEN
CY7B933 Receiver LogicBlockDiagram
B923–2
RF
A/B
INA+
INB(INB+)
SO
REFCLK
MODE
BISTEN
PECL
TTL
TEST
LOGIC
CLOCK
SYNC
CKR RDY
SC/D(Q
a
)
RVS(Q
j
)
Q
0
7
(Q
b
h
)
OUTPUT
REGISTER
DECODER
DECODER
REGISTER
SHIFTER
FRAMER
DATA
INA
SI(INB
)
CY7B923
CY7B933
2
Figure 1. HOTLink System Connections
PROTOCOL
LOGIC
HOST
TRANSMIT
MESSAGE
BUFFER
7B923
TRANSMITTER
SERIAL LINK
7B933
RECEIVER
RECEIVE
MESSAGE
BUFFER
PROTOCOL
LOGIC
HOST
B923–3
CY7B923 Transmitter Pin Configurations
SC/D(D
a
)
SVS(D
j
)
OUTB
OUTC
OUTC+
V
CCN
BISTEN
GND
MODE
RP
V
CCQ
(D
h
)D
7
(D
g
)D
6
(D
f
)D
5
(D
i
)D
4
OUTB+
OUTA+
OUTA
FOTO
ENN
ENA
V
CCQ
CKW
GND
D
0
(D
b
)
D
2
(D
d
)
D
1
(D
c
)
D
3
(D
e
)
B923–4
B923–5
43 12
28
8
9
7
6
5
22
21
23
24
25
1213 1514
16
PLCC/LCC
Top View
10
11
20
19
2726
1718
FOTO
ENN
ENA
V
CCQ
CKW
GND
SC/D
(D
a
)
BISTEN
GND
MODE
RP
V
CCQ
SVS(D
j
)
(D
h
)D
7
6
D
V
OUTC+
OUTC
OUTB+
OUTA+
OUTA
OUTB
SOIC
Top View
7B923
7B923
5
D
4
D
3
D
2
D
1
D
0
D
CCN
d
(D )
e
(D )
i
(D )
f
(D )
g
(D )
c
(D )
b
(D )
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
CY7B933 Receiver Pin Configurations
SC/D (Q
a
)
INA
INA+
A/B
BISTEN
RF
GND
RDY
GND
V
CCN
RVS(Q
j
)
(Q
h
)Q
7
(Q
g
)Q
6
(Q
f
)Q
5
(Q
i
)Q
4
INB(INB+)
SI(INB
)
MODE
REFCLK
V
CCQ
SO
CKR
V
CCQ
GND
SC/D (Q
a
)
Q
0
(Q
b
)
Q
2
(Q
d
)
Q
1
(Q
c
)
Q
3
(Q
e
)
B923–6
B923–7
43 12
28
8
9
7
6
5
22
21
23
24
25
1213 1514
16
PLCC/LCC
Top View
10
11
20
19
2726
1718
REFCLK
V
CCQ
SO
CKR
V
CCQ
GND
RF
GND
RDY
GND
V
CCN
RVS(Q
j
)
(Q
h
)Q
7
Q
Q
Q
Q
Q
Q
Q
BISTEN
A/B
INA+
INB (INB+)
SI (INB
)
MODE
INA
SOIC
Top View
7B933
7B933
6
5
4
3
2
1
0
d
(Q )
e
(Q )
i
(Q )
f
(Q )
g
(Q )
c
(Q )
b
(Q )
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
CY7B923
CY7B933
3
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature...................................... 65°C to +150°C
Ambient Temperature with
Power Applied..................................................55°C to +125°C
Supply Voltage to Ground Potential................. −0.5V to +7.0V
DC Input Voltage ................................................ 0.5V to +7.0V
Output Current into TTL Outputs (LOW)......................30 mA
Output Current into PECL outputs (HIGH)...................50 mA
Static Discharge Voltage ........................................... >4001V
(per MILSTD883, Method 3015)
Latch-Up Current..................................................... >200 mA
Pin Descriptions
Operating Range
Range
Ambient
Temperature
V
CC
Commercial 0
°
C to +70
°
C 5V ± 10%
Industrial
40°
C to +85
°
C 5V ± 10%
Military
55°
C to +125
°
C
Case Temperature
5V ± 10%
CY7B923 HOTLink Transmitter
Name I/O Description
D
0
7
(D
b
h
)
TTL In Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW
(or on the next rising CKW with ENN
LOW). If ENA and ENN are HIGH, a Null character (K28.5) is
sent. When MODE is HIGH, D
0, 1, ...7
become D
b, c,...h
respectively.
SC/D (D
a
) TTL In Special Character/Data Select. A HIGH on SC/D when CKW rises causes the transmitter to encode
the pattern on D
0
7
as a control code (Special Character), while a LOW causes the data to be coded
using the 8B/10B data alphabet. When MODE is HIGH, SC/D
(D
a
) acts as D
a
input. SC/D has the
same timing as D
0
7
.
SVS
(D
j
)
TTL In Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent
while the data on the parallel inputs is ignored. If SVS is LOW, the state of D
0
7
and SC/D determines
the code sent. In normal or test mode, this pin overrides the BIST generator and forces the trans-
mission of a Violation code. When MODE is HIGH (placing the transmitter in unencoded mode),
SVS (D
j
) acts as the D
j
input. SVS has the same timing as D
0
7
.
ENA TTL In Enable Parallel Data. If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and
sent. If ENA
and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null
character (K28.5) to fill the space between user data. ENA
may be held HIGH/LOW continuously or
it may be pulsed with each data byte to be sent. If ENA
is being used for data control, ENN will
normally be strapped HIGH, but can be used for BIST function control.
ENN TTL In Enable Next Parallel Data. If ENN is LOW, the data appearing on D
0
7
at the next rising edge of
CKW is loaded, encoded, and sent. If ENA
and ENN are HIGH, the data appearing on D
0
7
at the
next rising edge of CKW will be ignored and the Transmitter will insert a Null character to fill the space
between user data. ENN
may be held HIGH/LOW continuously or it may be pulsed with each data
byte sent. If ENN
is being used for data control, ENA will normally be strapped HIGH, but can be
used for BIST function control.
CKW TTL In Clock Write. CKW is both the clock frequency reference for the multiplying PLL that generates the
highspeed transmit clock, and the byte rate write signal that synchronizes the parallel data input.
CKW must be connected to a crystal controlled time base that runs within the specified frequency
range of the Transmitter and Receiver.
FOTO TTL In Fiber Optic Transmitter Off. FOTO determines the function of two of the three PECL transmitter
output pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs con-
tinuously. If FOTO is HIGH, OUTA± and OUTB± are forced to their “logic zero” state (OUT+ = LOW
and OUT = HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is
unaffected by the level on FOTO, and can be used as a loop-back signal source for board-level
diagnostic testing.
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