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CY62128ELL-45ZXI

Part # CY62128ELL-45ZXI
Description SRAM ASYNC SGL 5V 1MBIT 128KX8 45NS 32TSOP-I - Trays
Category IC
Availability In Stock
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CYPRESS SEMICONDUCTOR
Date Code: 0725
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05485 Rev. *E Revised May 07, 2007
CY62128E MoBL
®
1-Mbit (128K x 8) Static RAM
Features
• Very high speed: 45 ns
• Temperature ranges
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62128B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 4 µA (Industrial)
• Ultra low active power
— Typical active current: 1.3 mA @ f = 1 MHz
• Easy memory expansion with CE
1
, CE
2
and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC,
and 32-pin TSOP I packages
Functional Description
[1]
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW). The eight input and output pins (IO
0
through
IO
7
) are placed in a high impedance state when the device is
deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled
(OE
HIGH), or a write operation is in progress (CE
1
LOW and
CE
2
HIGH and WE LOW)
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appears on
the IO pins.
Logic Block Diagram
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
12
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A
10
A
11
CE
1
CE
2
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
[+] Feedback [+] Feedback
Document #: 38-05485 Rev. *E Page 2 of 11
CY62128E MoBL
®
Pin Configuration
[2]
Product Portfolio
Product Range V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating I
CC
(mA)
Standby I
SB2
(µA)
f = 1MHz f = f
max
Min Typ
[3]
Max Typ
[3]
Max Typ
[3]
Max Typ
[3]
Max
CY62128ELL Ind’l/Auto-A 4.5 5.0 5.5 45
[4]
1.3 2 11 16 1 4
CY62128ELL Auto-E 4.5 5.0 5.5 55 1.3 4 11 35 1 30
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
STSOP
Top View
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
26
25
26
27
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC
Top View
NC
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
V
SS
V
CC
CE
2
WE
OE
CE
1
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (t
AA
, t
ACE
) and 25 ns (t
DOE
) are guaranteed.
[+] Feedback [+] Feedback
Document #: 38-05485 Rev. *E Page 3 of 11
CY62128E MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground
Potential...............................–0.5V to 6.0V (V
CC(max)
+ 0.5V)
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
...............–0.5V to 6.0V (V
CC(max)
+ 0.5V)
DC Input Voltage
[5, 6]
...........–0.5V to 6.0V (V
CC(max)
+ 0.5V)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[7]
CY62128ELL Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
Auto-E –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Unit
Min Typ
[3]
Max Min Typ
[3]
Max
V
OH
Output HIGH
Voltage
I
OH
= –1 mA 2.4 2.4 V
V
OL
Output LOW
Voltage
I
OL
= 2.1 mA 0.4 0.4 V
V
IH
Input HIGH Voltage V
CC
= 4.5V to 5.5V 2.2 V
CC
+ 0.5 2.2 V
CC
+ 0.5 V
V
IL
Input LOW voltage V
CC
= 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V
I
IX
Input Leakage
Current
GND < V
I
< V
CC
–1 +1 –4 +4 µA
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
, Output Disabled –1 +1 –4 +4 µA
I
CC
V
CC
Operating
Supply Current
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
11 16 11 35 mA
f = 1 MHz 1.3 2 1.3 4
I
SB2
[8]
Automatic CE
Power down
Current—CMOS
Inputs
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC(max)
14 130µA
Capacitance (For all Packages)
[9]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
10 pF
C
OUT
Output Capacitance 10 pF
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 µs ramp time from 0 to V
CC
(min) and 200 µs wait time after V
CC
stabilization.
8. Only chip enables (CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
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