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CS5351-KSZ

Part # CS5351-KSZ
Description ADC DUAL DELTA-SIGMA 192KSPS24BIT SERL 24SOIC - Rail/Tube
Category IC
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CIRRUS LOGIC
Date Code: 0431
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
http://www.cirrus.com
108 dB, 192 kHz, Multi-bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
108 dB Dynamic Range
-98 dB THD+N
System Sampling Rates up to 192 kHz
135 mW Power Consumption
High-Pass Filter and DC Offset Calibration
Supports Logic Levels Between 5 and 2.5 V
Single-Ended Analog Inputs
Overflow Detection
Pin Compatible with the CS5361
General Description
The CS5351 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analog-
to-digital conversion, and anti-alias filtering. The device
generates 24-bit values for both left and right inputs in
serial form at sample rates up to 192 kHz per channel.
The CS5351 uses a 5th-order, multi-bit, delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The ADC uses a differential architecture which provides
excellent noise rejection.
The CS5351 is ideal for audio systems requiring wide
dynamic range, negligible distortion, and low noise.
Such applications include A/V receivers, DVD-R, CD-R,
digital mixing consoles, and effects processors.
ORDERING INFORMATION
CS5351-KSZ, Lead Free -10° to 70°C 24-pin SOIC
CS5351-KZZ, Lead Free -10° to 70°C 24-pin TSSOP
CS5351-DZZ, Lead Free -40° to 85°C 24-pin TSSOP
CDB5351 Evaluation Board
Voltage Reference
Serial Output Interface
Digital
Filter
High
Pass
Filter
High
Pass
Filter
Decimation
Digital
Filter
Decimation
DAC
-
+
S/H
DAC
-
+
S/H
AINR
SCLK
SDOUT MCLK
RST
VQ3
LRCK
AINL
FILT+
I²S/LJ
M/S
HPF
MODE0
MODE1
REFGND
V
L
MDIV
LP Filter
LP Filter
ΔΣ
ΔΣ
OVFL
VQ1
VQ2
MAY '07
DS565F2
CS5351
2 DS565F2
CS5351
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
SPECIFIED OPERATING CONDITIONS .............................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4
ANALOG CHARACTERISTICS (CS5351-KSZ/KZZ) ............................................................................. 5
ANALOG CHARACTERISTICS (CS5351-DZZ) .................................................................................... 6
DIGITAL FILTER CHARACTERISTICS .................................................................................................7
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10
DIGITAL CHARACTERISTICS ............................................................................................................ 10
THERMAL CHARACTERISTICS ......................................................................................................... 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT .............................................................. 11
2. PIN DESCRIPTIONS ............................................................................................................................ 14
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 15
4. APPLICATIONS ................................................................................................................................... 16
4.1 Operational Mode/Sample Rate Range Select .............................................................................. 16
4.2 System Clocking ............................................................................................................................ 16
4.2.1 Slave Mode ........................................................................................................................... 16
4.2.2 Master Mode ......................................................................................................................... 17
4.3 Power-Up Sequence ...................................................................................................................... 17
4.4 Analog Connections ....................................................................................................................... 18
4.5 High-Pass Filter and DC Offset Calibration ................................................................................... 18
4.6 Overflow Detection ......................................................................................................................... 19
4.6.1 OVFL Output Timing ............................................................................................................. 19
4.7 Grounding and Power Supply Decoupling ..................................................................................... 19
4.8 Synchronization of Multiple Devices .............................................................................................. 19
5. PARAMETER DEFINITIONS ................................................................................................................ 20
6. PACKAGE DIMENSIONS ................................................................................................................. 21
7. REVISION HISTORY ............................................................................................................................ 23
DS565F2 3
CS5351
LIST OF FIGURES
Figure 1. Single-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 2. Single-Speed Mode Transition Band ........................................................................................... 8
Figure 3. Single-Speed Mode Transition Band (Detail) ............................................................................... 8
Figure 4. Single-Speed Mode Passband Ripple ......................................................................................... 8
Figure 5. Double-Speed Mode Stopband Rejection .................................................................................... 8
Figure 6. Double-Speed Mode Transition Band .......................................................................................... 8
Figure 7. Double-Speed Mode Transition Band (Detail) ............................................................................. 9
Figure 8. Double-Speed Mode Passband Ripple ........................................................................................ 9
Figure 9. Quad-Speed Mode Stopband Rejection ...................................................................................... 9
Figure 10. Quad-Speed Mode Transition Band .......................................................................................... 9
Figure 11. Quad-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 12. Quad-Speed Mode Passband Ripple ........................................................................................ 9
Figure 13. Master Mode, Left-Justified SAI ............................................................................................... 12
Figure 14. Slave Mode, Left-Justified SAI ................................................................................................. 12
Figure 15. Master Mode, I²S SAI ............................................................................................................... 12
Figure 16. Slave Mode, I²S SAI ................................................................................................................. 12
Figure 17. OVFL Output Timing ................................................................................................................ 12
Figure 18. Left-Justified Serial Audio Interface ......................................................................................... 13
Figure 19. I²S Serial Audio Interface ......................................................................................................... 13
Figure 20. OVFL Output Timing, I²S Format ............................................................................................. 13
Figure 21. OVFL Output Timing, Left-Justified Format ............................................................................. 13
Figure 22. Typical Connection Diagram .................................................................................................... 15
Figure 23. CS5351 Master Mode Clocking ............................................................................................... 17
Figure 24. CS5351 Recommended Analog Input Buffer ........................................................................... 18
LIST OF TABLES
Table 1. CS5351 Mode Control ................................................................................................................. 16
Table 2. CS5351 Slave Mode Clock Ratios .............................................................................................. 16
Table 3. CS5351 Common Master Clock Frequencies ............................................................................. 17
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