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CS496122-CQZ

Part # CS496122-CQZ
Description 16X16 IC W/DSP C-NET INTERFACE PROC
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

16 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.3 Characteristics and Specifications
4.3.1 Absolute Maximum Ratings
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
4.3.2 Recommended Operating Conditions
4.3.3 Digital DC Characteristics
(measurements performed under static conditions.)
4.3.4 Power Supply Characteristics
(measurements performed under operating conditions))
NOTES:1. Dependent on application firmware and DSP clock speed.
Parameter Symbol Min Max Unit
DC power supplies: Core supply
PLL supply
I/O supply
|VDDA – VDD|
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
-
2.0
2.0
5.0
0.3
V
V
V
V
Input current, any pin except supplies I
in
-+/- 10mA
Input voltage on FILT1, FILT2 V
filt
2.0 V
Input voltage on I/O pins V
inio
-5.0V
Storage temperature T
stg
–65 150 °C
Parameter Symbol Min Typ Max Unit
DC power supplies: Core supply
PLL supply
I/O supply
|VDDA – VDD|
VDD
VDDA
VDDIO
1.71
1.71
3.13
1.8
1.8
3.3
1.89
1.89
3.46
0.3
V
V
V
V
Ambient operating temperature
- CQ
- DQ
T
A
0
- 40
-
+ 70
+ 85
°C
Parameter Symbol Min Typ Max Unit
High-level input voltage V
IH
2.0 - - V
Low-level input voltage, except XTI V
IL
--0.8V
Low-level input voltage, XTI V
ILXTI
--0.6V
Input Hysteresis V
hys
0.3 V
High-level output voltage at
I
O
= –8.0 mA
O
= –16.0 mA
V
OH
VDDIO * 0.9 - - V
Low-level output voltage at
I
O
= 8.0 mA
O
= –16.0 mA
V
OL
--VDDIO * 0.1V
Input leakage current (all pins without internal pull-
up resistors except XTI)
I
IN
--5µA
Input leakage current (pins with internal pull-up
resistors, XTI)
I
IN-PU
--50µA
Parameter Min Typ Max Unit
Power supply current:
Core and I/O operating: VDD (Note 1)
PLL operating: VDDA
With external memory and most ports operating: VDDIO
-
-
-
500
10
120
-
-
-
mA
mA
mA
CobraNet Hardware User’s Manual
Synchronization
DS651UM23 ©Copyright 2005 Cirrus Logic, Inc. 17
Version 2.3
5.0 Synchronization
Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design
(CM-2). This circuitry allows the synchronization modes documented below to be
achieved. Modes are distinguished by different settings of the multiplexors and software
elements.
Figure 3. Audio Clock Sub-system
5.1 Synchronization Modes
Clock synchronization mode for conductor and performer roles is independently
selectable via management interface variables syncConductorClock and
syncPerformerClock. The role (conductor or performer) is determined by the network
environment including the conductor priority setting of the device and the other devices on
the network. It is possible to ensure you will never assume the conductor role by selecting
a conductor priority of zero. However, it is not reasonable to assume that by setting a high
conductor priority, you will always assume the conductor role. For more information, refer
to CobraNet Programmer’s Reference Manual.
VCXO
24.576 MHz
MCLK_OUT
MCLK_IN
MCLK_SEL
AClkConfig
RefClkEnable
RefClkPolarity
REFCLK_IN
Legend:
External
Software
Component
Hardware
Component
(CM2)
Internal
Hardware
Component
(CS1810xx, CS4961xx)
CS1810xx/CS4961xx
DAC
FS1
SLCK
Phase
Detector
Loop
Filter
Sample
Phase
Counter
Edge
Detect
Audio
Clock
Generator
BeatReceived
18 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
Synchronization
The following synchronization modes are further described below:
"Internal Mode" on page 18
"External Word Clock Mode" on page 18
"External Master Clock Mode" on page 18
5.1.1 Internal Mode
All CobraNet clocks are derived from the onboard VCXO. The master clock generated by
the VCXO is available to external circuits via the master clock output.
Conductor—The VCXO is “parked” according to the syncClockTrim setting.
Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.
5.1.2 External Word Clock Mode
All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an
external clock supplied to the reference clock input. The clock supplied can be any
integral division of the sample clock in the range of 750Hz to 48kHz.
External synchronization lock range: ±5 µs. This specification indicates drift or wander
between the supplied clock and the generated network clock at the conductor. Absolute
phase difference between the supplied reference clock and generated sample clock is
dependant on network topology.
Conductor—This mode gives a means for synchronizing an entire CobraNet network to
an external clock.
Performer—The interface disregards the fine timing information delivered over the
network from the conductor. Coarse timing information from the conductor is still used;
fine timing information is instead supplied by the reference clock. The external clock
source must be synchronous with the network conductor. This mode is useful in
installations where a house sync source is readily available.
5.1.3 External Master Clock Mode
The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a
“hard” synchronization mode. The supplied clock is used directly by the CobraNet
interface for all timing. This mode is primarily useful for devices with multiple CobraNet
interfaces sharing a common master audio clock. The supplied clock must be
24.576 MHz. The supplied clock must have a ±37 ppm precision.
Conductor—The entire network is synchronized to the supplied master clock.
Performer—The node will initially lock to the network clock and will “jam sync” via the
supplied master clock. The external clock source must be synchronous with the network
conductor.
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