CS4344/5/6/8

DS613PP2 7

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The

filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample

rate by multiplying the given characteristic by Fs.) (See note 6)

Notes: 2. Response is clock dependent and will scale with Fs.

3. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.

For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.

For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

4. Refer to Figure 2.

5. De-emphasis is available only in Single Speed Mode.

6. Amplitude vs. Frequency plots of this data are available in “Appendix” on page 21.

Parameter Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response Single Speed Mode

Passband (Note 2) to -0.05 dB corner

to -3 dB corner

.4780

.4996

Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB

StopBand .5465 - - Fs

StopBand Attenuation (Note 3) 50 - - dB

Group Delay tgd - 10/Fs - s

De-emphasis Error (Note 5) Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+1.5/+0

+.05/-.25

-.2/-.4

Combined Digital and On-chip Analog Filter Response Double Speed Mode

Passband (Note 2) to -0.1 dB corner

to -3 dB corner

.4650

.4982

Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB

StopBand .5770 - - Fs

StopBand Attenuation (Note 3) 55 - - dB

Group Delay tgd - 5/Fs - s

Combined Digital and On-chip Analog Filter Response Quad Speed Mode

Passband (Note 2) to -0.1 dB corner

to -3 dB corner

0.397

0.476

Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB

StopBand 0.7 - - Fs

StopBand Attenuation (Note 3) 51 - - dB

Group Delay tgd - 2.5/Fs - s

CS4344/5/6/8

8 DS613PP2

DIGITAL INPUT CHARACTERISTICS

7. I

for LRCK is ±20 µA max.

POWER AND THERMAL CHARACTERISTICS

8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are

based on highest FS and highest MCLK. Variance between speed modes is small.

9. Power down mode is defined when all clock and data lines are held static.

10. Valid with the recommended capacitor values on VQ and FILT+

as shown in the typical connection

diagram in Section 3.

Parameters Symbol Min Typ Max Units

High-Level Input Voltage (% of VA) V

55% - - V

Low-Level Input Voltage (% of VA) V

--30%V

Input Leakage Current (Note 7) I

--±10µA

Input Capacitance - 8 - pF

5V Nom 3.3V Nom

Parameters Symbol Min Typ Max Min Typ Max Units

Power Supplies

Power Supply Current normal operation

(Note 8) power-down state (Note 9)

220

100

µA

Power Dissipation normal operation

power-down state (Note 9)

110

1.1

150

0.33

Package Thermal Resistance θ

-95- -95-°C/Watt

Power Supply Rejection Ratio (Note 8) (1 kHz)

(60 Hz)

PSRR -

AOUTx

AGND

3.3 µF

out

Figure 1. Output Test Load

100

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

Resistive Load -- R (k

Ω

)

125

Figure 2. Maximum Loading

CS4344/5/6/8

DS613PP2 9

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

Notes: 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on

page 12 for supported ratio’s and frequencies.

12. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.

13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and

MCLK/LRCK ratio. (See figures 7-9)

Parameters Symbol Min Typ Max Units

MCLK Frequency 0.512 - 50 MHz

MCLK Duty Cycle 45 - 55 %

Input Sample Rate All MCLK/LRCK ratios combined

(Note 11) 256x, 384x, 1024x

256x, 384x

512x, 768x

1152x

128x, 192x

64x, 96x

128x, 192x

Fs 2

100

168

200

134

100

200

kHz

External SCLK Mode

LRCK Duty Cycle (External SCLK only) 45 50 55 %

SCLK Pulse Width Low t

sclkl

20 - - ns

SCLK Pulse Width High t

sclkh

20 - - ns

SCLK Duty Cycle 45 50 55 %

SCLK rising to LRCK edge delay t

slrd

20 - - ns

SCLK rising to LRCK edge setup time t

slrs

20 - - ns

SDIN valid to SCLK rising setup time t

sdlrs

20 - - ns

SCLK rising to SDIN hold time t

sdh

20 - - ns

Internal SCLK Mode

LRCK Duty Cycle (Internal SCLK only) (Note 12) - 50 - %

SCLK Period (Note 13) t

sclkw

--ns

SCLK rising to LRCK edge t

sclkr

--µs

SDIN valid to SCLK rising setup time t

sdlrs

--ns

SCLK rising to SDIN hold time

MCLK / LRCK =1152, 1024, 512, 256, 128, or 64

sdh

--ns

SCLK rising to SDIN hold time

MCLK / LRCK = 768, 384, 192, or 96

sdh

--ns

SCLK

-----------------

tsclkw

------------------

512()Fs

----------------------10+

512()Fs

----------------------15+

384()Fs

----------------------15+

Part #	CS4344-CZZ
Description	DAC DUAL DELTA-SIGMA 24BIT 10TSSOP - Rail/Tube
Category	IC
Availability	Out of Stock
Qty	0

CS4344-CZZ

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Technical Document