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CS4210VJG

Part # CS4210VJG
Description IC CONTROLLER GEODE OHCI 100LQFP
Category IC
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Technical Document


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© 2000 National Semiconductor Corporation www.national.com
Geode™ CS4210 IEEE 1394 OHCI Controller
General Description
The National Semiconductor
®
Geode™ CS4210 is a PCI-
based IEEE 1394 OHCI (Open Host Controller Interface)
controller. The CS4210 provides an implementation of the
IEEE 1394 Link Layer functionality according to the pro-
gramming model defined by 1394 OHCI Specification Ver-
sion 1.0. It supports high speed serial communication up to
400 Mbits per second.
The CS4210 is an implementation of the link layer protocol
of the IEEE 1394 high speed serial bus, with additional fea-
tures to support the transaction and bus management lay-
ers. The CS4210 also includes DMA engines for high
speed performance data transfer and a host PCI bus inter-
face. Perfect for use in PC, set-top box, thin client, and
WebPAD™ system applications.
The CS4210 supports two types of data transfers: asyn-
chronous and isochronous.
The CS4210 provides an external IEEE 1394 physical layer
device interface. The CS4210’s physical layer interface
(PHY-Link) is compatible with the Geode™ CS4103 and
other IEEE 1394 physical layer devices.
Features
Supports 100, 200, and 400 Mbit/sec data transfer rates
Compliant with 1394 OHCI Specification Version 1.0
Compatible interface with the Geode CS4103 IEEE
P1394a Physical Layer (PHY) device and other IEEE
1394-1995 version and P1394a Draft 2.0 Physical Layer
devices
Eight isochronous transmit contexts
Eight isochronous receive contexts
Capable of reading a 128-byte descriptor in one burst
128 byte, zero wait state bursting
Dynamically re-prioritize services
2 KB of isochronous transmit FIFO
2 KB of asynchronous transmit FIFO
4 KB of receiver FIFO
Per-packet FIFO thresholding
Four concurrent posted writes
Eight pending physical responses
National specific configuration registers
I
2
C interface support for an optional serial EEPROM
Accepts and generates external 8 kHz reference clock
5V tolerant PCI rev 2.1 I/O interface
0.25µ CMOS
100-pin LQFP (Low-profile Quad Flat Pack) package
NAND tree for test purposes
System Block Diagram
Geode™ CS4210
IEEE 1394
OHCI Controller
Geode™ CS4103
P1394a
Physical Layer
EEPROM
I
2
C Interface
PCI Interface
PHY-Link Interface
PCI Bus
IEEE 1394
Cable
Connectors
July 2000
Geode™ CS4210 IEEE 1394
OHCI Controller
National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
www.national.com 2 Revision 1.0
Geode™ CS4210
Table of Contents
1.0 ArchitecturalDescription.............................................6
1.1 PCIINTERFACEMODULE ....................................................6
1.2 DMAENGINE...............................................................6
1.2.1 TransferEngine ......................................................7
1.2.2 HostMemoryOrganization .............................................7
1.2.3 ATDMA .............................................................7
1.2.4 ITDMA .............................................................7
1.2.5 RDMA..............................................................7
1.3 TRANSMITDRAIN ...........................................................7
1.4 RECEIVEFILL ..............................................................7
1.5 LINKLAYER................................................................7
1.6 PHYSICALLAYERINTERFACE ................................................7
1.7 REGISTERSET .............................................................7
1.8 RELATEDDOCUMENTS......................................................7
2.0 SignalDefinitions...................................................8
2.1 PINASSIGNMENT...........................................................8
2.2 SIGNALDESCRIPTIONS ....................................................12
2.2.1 PCIBusInterfaceSignals .............................................12
2.2.2 PHY-LinkInterfaceSignals.............................................13
2.2.3 Miscellaneous Interface Signals . . . . . . . . . . . ..............................14
2.2.4 PowerSuppliesandGroundConnections .................................14
3.0 OperationalDescription.............................................15
3.1 OVERVIEW ...............................................................15
3.1.1 AsynchronousDataTransferFunctions ...................................15
3.1.2 IsochronousDataTransferFunctions.....................................15
3.1.3 Miscellaneous Functions ..............................................15
3.2 SOFTWAREINTERFACEOVERVIEW ..........................................16
3.2.1 Registers ..........................................................16
3.2.2 DMAOperation .....................................................16
3.2.2.1 DMAMemory.......................................................16
3.2.2.2 PhysicalResponseDMA ..............................................16
3.2.3 Interrupts ..........................................................16
3.2.3.1 AsynchronousTransmitInterrupts.......................................16
3.2.3.2 AsynchronousReceiveInterrupts........................................16
3.2.3.3 IsochTxandRxContextInterrupts ......................................17
3.3 COMMONDMACONTROLLERFEATURES .....................................19
3.3.1 ContextRegisters....................................................19
3.3.2 ContextControl.event .................................................19
3.3.2.1 ContextControl.run...................................................21
3.3.2.2 ContextControl.wake .................................................21
3.3.2.3 ContextControl.active.................................................21
3.3.2.4 ContextControl.dead..................................................21
3.3.2.5 CommandPtr .......................................................22
3.4 LISTMANAGEMENT ........................................................23
3.4.1 ContextInitialization ..................................................23
3.4.2 AppendingtoRunningList .............................................23
3.4.3 Stopping a Context . . . . . ..............................................23
3.4.4 HardwareBehavior...................................................23
Revision 1.0 3 www.national.com
Geode™ CS4210
Table of Contents (Continued)
3.5 ASYNCHRONOUS RECEIVE . . . ..............................................23
3.5.1 UnrecoverableError ..................................................24
3.5.2 AckCodesforWriteRequests ..........................................24
3.5.3 PostedWrites.......................................................24
3.5.4 Retries ............................................................25
3.5.5 DMASummary......................................................25
3.6 PHYSICALREQUESTS......................................................26
3.6.1 FilteringPhysicalRequests ............................................26
3.6.2 PostedWrites.......................................................27
3.6.3 PhysicalResponses..................................................27
3.6.4 PhysicalResponseRetries ............................................27
3.6.5 InterruptConsiderationsforPhysicalRequests .............................27
3.6.6 BusReset..........................................................27
3.7 HOSTBUSERRORS........................................................28
3.7.1 CausesofHostBusErrors.............................................28
3.7.2 CS4210ActionsWhenHostBusErrorOccurs .............................28
3.7.2.1 DescriptorReadError.................................................28
3.7.2.2 xferStatusWriteError.................................................28
3.7.2.3 TransmitDataReadError..............................................28
3.7.3 IsochronousTransmitDataWriteError ...................................29
3.7.4 AsynchronousReceiveDMADataWriteError..............................29
3.7.5 IsochronousReceiveDataWriteError....................................29
3.7.6 PhysicalReadError ..................................................29
3.7.7 PostedWriteError ...................................................29
3.8 BUSRESETS..............................................................30
3.8.1 AsynchronousTransmit ...............................................30
3.8.2 AsynchronousReceive................................................30
3.8.3 IsochronousTransmitandReceive ......................................30
3.9 SERIALEEPROM ..........................................................31
3.9.1 Serial EEPROM Cyclic Redundancy Check . . ..............................31
4.0 RegisterDescriptions...............................................33
4.1 PCICONFIGURATIONSPACEACCESS ........................................33
4.2 REGISTERSUMMARY ......................................................34
4.3 PCICONFIGURATIONREGISTERS............................................40
4.4 OHCICONFIGURATIONREGISTERS ..........................................48
4.4.1 VersionRegister.....................................................58
4.4.2 GUIDROMRegister ..................................................58
4.4.3 ATRetriesRegister ...................................................59
4.4.4 AutonomousCSRResources ..........................................60
4.4.5 ConfigurationROMHeaderRegister .....................................61
4.4.6 BusIdentificationRegister .............................................61
4.4.7 BusOptionsRegister .................................................62
4.4.8 GlobalUniqueIDRegister .............................................63
4.4.9 ConfigurationROMMappingRegister ....................................63
4.4.10 PostedWriteAddressRegister ..........................................64
4.4.11 VendorIDRegister...................................................64
4.4.12 HCControl Register . . . . ..............................................65
4.4.12.1 noByteSwapData....................................................66
4.4.12.2 programPhyEnableandaPhyEnhanceEnable..............................67
4.4.12.3 LPSandlinkEnable ..................................................67
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