CobraNet Hardware User’s Manual

Digital Audio Interface

Version 2.3

6.0 Digital Audio Interface

The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional

synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional

synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as

the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial

data includes two (or four) audio channels. CobraNet supports two synchronous serial bit

rates: 48 Khz and 96 KHz. However, 96 kHz sample rate is not available when using

CS18102x/CS49612x with 16X16 channels. Bit rate is selected by the modeRateControl

variable. All synchronous serial interfaces operate from a common clock at the same bit

rate.

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x &

CS18101x/CS49611x

Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x

Default channel ordering is shown above. Note that the first channel always begins after

the rising or falling edge of FS1 (depending on the mode).

DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are

received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are

transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant

(sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits

15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic

recommends driving unused LS bits to zero.

1 2

FS1

DAO1_DATA0 / DAI1_DATA0

3 4

5 6

7 8

DAO1_DATA1 / DAI1_DATA1

DAO1_DATA2 / DAI1_DATA2

DAO1_DATA3 / DAI1_DATA3

* Not

resent in CS18100x or CS49610x.

1 2

FS1

DAO1_DATA0 / DAI1_DATA0

5 6

9 10

13 14

DAO1_DATA1 / DAI1_DATA1

DAO1_DATA2 / DAI1_DATA2

DAO1_DATA3 / DAI1_DATA3

3 4

7 8

11 12

15 16

Version 2.3

CobraNet Hardware User’s Manual

Digital Audio Interface

Although data is always transmitted and received with a 32-bit resolution by the

synchronous serial ports, the resolution of the data transferred to/from the Ethernet may

be less. Incoming audio data is truncated to the selected resolution. Unused least

significant bits on outgoing data is zero filled.

6.1 Digital Audio Interface Timing

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1

An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows

a MCLK_OUT edge by 0.0 to 10.0ns.

Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or

the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends

on power up timing.

Figure 7. Serial Port Data Timing Overview

Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to

the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the

edge of DAO1_SCLK.

MCLK_OUT

DAO1_SCLK

FS1

–

5ns

–

10ns

DAI1_DATAx

DAO1_SCLK

–

12ns

DAO1_DATAx

≥5ns ≥0ns

CobraNet Hardware User’s Manual

Digital Audio Interface

Version 2.3

6.1.1 Normal Mode Data Timing

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The

figure above shows 24-bit audio data.

The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of

DAI_SCLK and data changes on the falling edge.

6.1.2 I

S Mode Data Timing

Figure 10. Audio Data Timing Detail - I

S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

Figure 11. Audio Data Timing Detail - I

S Mode, 128FS - CS18102x & CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The

figure above shows 24-bit audio data.

The MSB is left justified and arrives one bit period following FS1. Data is sampled on the

rising edge of DAI_SCLK and data changes on the falling edge.

FS1

DAI1_DATAx

DAO1_DATAx

DAI1_SCLK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 231 0 Unused

FS1

DAI1_DATAx

DAO1_DATAx

DAI1_SCLK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 231 0 Unused 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2

1 0 Unused

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 231 0 Unused 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2

1 0 Unused

FS1

DAI1_DATAx

DAO1_DATAx

DAI1_SCLK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 231 0 Unused

FS1

DAI1_DATAx

DAO1_DATAx

DAI1_SCLK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 231 0 Unused 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2

1 0 Unused

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 231 0 Unused 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2

1 0 Unused

Part #	CS181022-CQZ
Description	16X16 CHANNEL W/O DSP C-NET INTERFACE PROC. PB FREE - Tray
Category	IC
Availability	In Stock
Qty	15

Qty	Price
1 - 3	$24.90634
4 - 6	$19.81186
7 - 9	$18.67976
10 - 12	$17.35896
13 +	$15.47212

Manufacturer	Available	Qty
CIRRUS LOGIC Date Code: 0710	Freelance Stock: 2 Ships Immediately
CIRRUS LOGIC Date Code: 0637	Freelance Stock: 7 Ships Immediately
CIRRUS LOGIC Date Code: 0710	Freelance Stock: 6 Ships Immediately

CS181022-CQZ

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