Name: CD54HCT138F3A
SKU: CD54HCT138F3A
Price: 5.44767 USD
Availability: OutOfStock

Data sheet acquired from Harris Semiconductor

SCHS147I

Features

• Select One Of Eight Data Outputs

Active Low for 138, Active High for 238

• l/O Port or Memory Selector

• Three Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13 ns at V

= 5 V,

= 15 pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2 V to 6 V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5 V

• HCT Types

- 4.5-V to 5.5-V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8 V (Max), V

= 2 V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed

silicon-gate CMOS decoders well suited to memory address

decoding or data-routing applications. Both circuits feature

low power consumption usually associated with CMOS

circuitry, yet have speeds comparable to low-power Schottky

TTL logic. Both circuits have three binary select inputs (A0,

A1, and A2). If the device is enabled, these inputs determine

which one of the eight normally high outputs of the

HC/HCT138 series go low or which of the normally low

outputs of the HC/HCT238 series go high.

Two active low and one active high enables (

E1, E2, and E3)

are provided to ease the cascading of decoders. The

decoder’s eight outputs can drive ten low-power Schottky

TTL equivalent loads.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC138F3A -55 to 125 16 Ld CERDIP

CD54HC238F3A -55 to 125 16 Ld CERDIP

CD54HCT138F3A -55 to 125 16 Ld CERDIP

CD54HCT238F3A -55 to 125 16 Ld CERDIP

CD74HC138E -55 to 125 16 Ld PDIP

CD74HC138M -55 to 125 16 Ld SOIC

CD74HC138MT -55 to 125 16 Ld SOIC

CD74HC138M96 -55 to 125 16 Ld SOIC

CD74HC238E -55 to 125 16 Ld PDIP

CD74HC238M -55 to 125 16 Ld SOIC

CD74HC238MT -55 to 125 16 Ld SOIC

CD74HC238M96 -55 to 125 16 Ld SOIC

CD74HC238NSR -55 to 125 16 Ld SOP

CD74HC238PW -55 to 125 16 Ld TSSOP

CD74HC238PWR -55 to 125 16 Ld TSSOP

CD74HC238PWT -55 to 125 16 Ld TSSOP

CD74HCT138E -55 to 125 16 Ld PDIP

CD74HCT138M -55 to 125 16 Ld SOIC

CD74HCT138MT -55 to 125 16 Ld SOIC

CD74HCT138M96 -55 to 125 16 Ld SOIC

CD74HCT238E -55 to 125 16 Ld PDIP

CD74HCT238M -55 to 125 16 Ld SOIC

CD74HCT238M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

October 1997 - Revised August 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC138, CD54/74HCT138,

CD54/74HC238, CD54/74HCT238

High-Speed CMOS Logic 3- to 8-Line Decoder/

Demultiplexer Inverting and Noninverting

[ /Title

(CD74

HC138

D74

HCT13

CD74

HC238

D74

HCT23

/Sub-

ject

(High

Speed

Pinout

CD54HC138, CD54HCT138, CD54HC238, CD54HCT238

(CERDIP)

CD74HC138, CD74HCT138, CD74HCT238

(PDIP, SOIC)

CD74HC238

(PDIP, SOIC, SOP, TSSOP)

TOP VIEW

Signal names in parentheses are for ’HC138 and ’HCT138.

Functional Diagram

GND

(Y7) Y7

Y1 (Y1)

Y2 (

Y2)

Y3 (

Y3)

Y4 (

Y4)

Y5 (

Y5)

Y6 (

Y6)

Y0 (

Y0)

A0 Y0

HC/HCT

238

HC/HCT

138

TRUTH TABLE ’HC138, ’HCT138

INPUTS

OUTPUTSENABLE ADDRESS

E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

XXHXXXHHHHHHHH

LXXXXXHHHHHHHH

XHXXXXHHHHHHHH

HLLLLLLHHHHHHH

HL L L LHHLHHHHHH

HL L LHLHHLHHHHH

HL L LHHHHHLHHHH

HL LHL LHHHHLHHH

HL LHLHHHHHHLHH

HL LHHLHHHHHHLH

HL LHHHHHHHHHHL

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

TRUTH TABLE ’HC238, ’HCT238

INPUTS

OUTPUTSENABLE ADDRESS

E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

XXHXXXLLLLLLLL

LXXXXXLLLLLLLL

XHXXXXLLLLLLLL

HLLLLLHLLLLLLL

HLLLLHLHLLLLLL

HLLLHLLLHLLLLL

HLLLHHLLLHLLLL

HLLHLLLLLLHLLL

HLLHLHLLLLLHLL

HLLHHLLLLLLLHL

HLLHHHLLLLLLLH

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For V

> -0.5V or V

< V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC V

or Ground Current, I

CC or

GND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (T

) . . . . . . . . . . . . . . . . . . . . . -55

C to 125

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

, V

. . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Package Thermal Impedance, θ

(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

C/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

C/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

C/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108

C/W

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

(V)

C -40

C TO 85

C -55

C TO 125

UNITSV

(V) I

(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

or V

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

or V

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current

GND

-6--±0.1 - ±1-±1 µA

Quiescent Device

Current

GND

0 6 - - 8 - 80 - 160 µA

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238

Part #	CD54HCT138F3A
Description	3 LINE TO 8 LINE DECODER/DEMUX, 16PIN CDIP
Category	IC
Availability	Out of Stock
Qty	0

CD54HCT138F3A

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