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CD54HC75F3A

Part # CD54HC75F3A
Description 4-BIT LATCH/4-TO-16 LINE DECODER
Category IC
Availability In Stock
Qty 8
Qty Price
1 - 1 $13.38488
2 - 3 $10.64706
4 - 5 $10.03866
6 - 6 $9.32886
7 + $8.31485
Manufacturer Available Qty
RCA
Date Code: 8723
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
Data sheet acquired from Harris Semiconductor
SCHS135F
Features
True and Complementary Outputs
Buffered Inputs and Outputs
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1µA at V
OL
, V
OH
Description
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent
latches. Each one of the 2-bit latches is controlled by
separate Enable inputs (
1E and 2E) which are active LOW.
When the Enable input is HIGH data enters the latch and
appears at the Q output. When the Enable input (
1E and 2E)
is LOW the output is not affected.
Pinout
CD54HC75, CD54HCT75 (CERDIP)
CD74HC75 (PDIP, SOIC, SOP, TSSOP)
CD74HCT75 (PDIP, SOIC, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC75F3A -55 to 125 16 Ld CERDIP
CD54HCT75F3A -55 to 125 16 Ld CERDIP
CD74HC75E -55 to 125 16 Ld PDIP
CD74HC75M -55 to 125 16 Ld SOIC
CD74HC75MT -55 to 125 16 Ld SOIC
CD74HC75M96 -55 to 125 16 Ld SOIC
CD74HC75NSR -55 to 125 16 Ld SOP
CD74HC75PW -55 to 125 16 Ld TSSOP
CD74HC75PWR -55 to 125 16 Ld TSSOP
CD74HCT75E -55 to 125 16 Ld PDIP
CD74HCT75M -55 to 125 16 Ld SOIC
CD74HCT75PWT -55 to 125 16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1Q0
1D0
1D1
2E
V
CC
2D0
2Q1
2D1
1Q0
1Q1
1E
GND
2Q0
2Q0
2Q1
1Q1
March 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC75, CD74HC75,
CD54HCT75, CD74HCT75
Dual 2-Bit Bistable
Transparent Latch
[
/Title
(
CD74
H
C75,
C
D74
H
CT75
)
/
Sub-
j
ect
(
Dual
2
-Bit
B
istabl
e
2
Functional Diagram
Logic Diagram
TRUTH TABLE
INPUTS OUTPUTS
D EQQ
LHLH
HHHL
XLQ0Q0
H= High Level
L= Low Level
X= Don’t Care
Q0 = The level of Q before the transition of E.
D0
2 (6)
3 (7)
16 (10)
Q1
Q0
D1
13 (4)
E
1 (11)
14 (8)
15 (9)
Q0
Q1
1 OF 2
LATCHES
FIGURE 1. LOGIC DIAGRAM FIGURE 2. LATCH DETAIL
D0
3 (7)
2 (6)
LATCH 0
QD
LE LE
16 (10)
1 (11)
Q0
Q0
E
13 (4)
LATCH 1
QD
LE LE
D1
14 (8)
Q1
15 (9)
Q1
5
12
GND
V
CC
P
N
LE
LE Q
P
N
LE
LE
Q
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θ
JA
(see Note 1)
E (PDIP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
o
C/W
M (SOIC) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
o
C/W
NS (SOP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
o
C/W
PW (TSSOP) package. . . . . . . . . . . . . . . . . . . . . . . . . .108
o
C/W
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02 2 1.9 - - 1.9 - 1.9 - V
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
---------V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02 2 - - 0.1 - 0.1 - 0.1 V
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
---------V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
V
CC
or
GND
-6--±0.1 - ±1-±1 µA
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75
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