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CD54HC4040F

Part # CD54HC4040F
Description 12-STAGE BINARY COUNTER - Rail/Tube
Category IC
Availability In Stock
Qty 43
Qty Price
1 - 9 $5.99997
10 - 18 $4.77270
19 - 27 $4.49998
28 - 36 $4.18180
37 + $3.72725
Manufacturer Available Qty
Harris Corporation
Date Code: 9232
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Harris Corporation
Date Code: 9901
  • Shipping Freelance Stock: 24
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Harris Corporation
Date Code: 9723
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RCA
Date Code: 8745
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RCA
Date Code: 8541
  • Shipping Freelance Stock: 2
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RCA
Date Code: 8732
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
Data sheet acquired from Harris Semiconductor
SCHS203D
Features
Fully Static Operation
Buffered Inputs
Common Reset
Negative Edge Pulsing
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1µA at V
OL
, V
OH
Description
The ’HC4040 and ’HCT4040 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Pinout
CD54HC4040, CD54HCT4040
(CERDIP)
CD74HC4040
(PDIP, SOIC, SOP)
CD74HCT4040
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC4040F3A -55 to 125 16 Ld CERDIP
CD54HCT4040F3A -55 to 125 16 Ld CERDIP
CD74HC4040E -55 to 125 16 Ld PDIP
CD74HC4040M -55 to 125 16 Ld SOIC
CD74HC4040MT -55 to 125 16 Ld SOIC
CD74HC4040M96 -55 to 125 16 Ld SOIC
CD74HC4040NSR -55 to 125 16 Ld SOP
CD74HCT4040E -55 to 125 16 Ld PDIP
CD74HCT4040M -55 to 125 16 Ld SOIC
CD74HCT4040MT -55 to 125 16 Ld SOIC
CD74HCT4040M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q
12
Q
6
Q
5
Q7
Q
4
Q
3
GND
Q
2
V
CC
Q
10
Q
8
Q
9
MR
CP
Q
1
Q
11
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC4040, CD74HC4040,
CD54HCT4040, CD74HCT4040
High-Speed CMOS Logic
12-Stage Binary Counter
[
/Title
(
CD74H
C
4040,
C
D74HC
T
4040)
/
Subject
(
High
S
peed
C
MOS
L
ogic
1
2-Stage
B
inary
2
Functional Diagram
9
6
3
4
14
1
15
12
10
INPUT
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
11
MASTER
Q
9
Q
10
Q
11
Q
12
7
5
2
13
8
GND
V
CC
16
PULSES
RESET
BUFFERED
OUTPUTS
12-STAGE
RIPPLE
COUNTER
TRUTH TABLE
CP COUNT MR OUTPUT STATE
L No Change
L Advance to Next State
X H All Outputs Are Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
= Transition from Low to High Level, = Transition from High to Low.
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040
3
Logic Diagram
9
Q
1
CP Q
CP
Q
I
R
Q’
CP Q
CP
Q
2
R
CP Q
CP
Q
3
R
CP Q
CP
Q
4
R
5
Q
4
CP Q
CP
Q
5
R
3
Q
5
CP Q
CP
Q
6
R
2
Q
6
CP Q
CP
Q
7
R
4
Q
7
CP Q
CP
Q
8
R
13
Q
8
CP Q
CP
Q
9
R
12
Q
9
CP Q
CP
Q
10
R
14
Q
10
CP Q
CP
Q
12
R
15
Q
11
CP Q
CP
Q
11
R
1
Q
12
CP
MR
11
10
7
Q
2
6
Q
3
CD54/74HC4040, CD54/74HCT4040
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