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CD54HC374F3A

Part # CD54HC374F3A
Description Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-
Category IC
Availability In Stock
Qty 85
Qty Price
1 - 17 $15.44168
18 - 35 $12.28315
36 - 53 $11.58126
54 - 71 $10.76238
72 + $9.59256
Manufacturer Available Qty
RCA
Date Code: 8600
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RCA
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RCA
Date Code: 8713
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RCA
Date Code: 8806
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

7
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
t
r
C
L
t
f
C
L
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V
1.3V
1.3V
1.3V
90%
10%
1.3V
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
1.3V
t
H(H)
1.3V
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
8
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms t
PLZ
and t
PZL
are the same as those for three-state shown on the left. The test circuit is Output R
L
=1kΩ to
V
CC
, C
L
= 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms (Continued)
50%
10%
90%
GN
D
V
CC
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns 6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
0.3
2.7
GN
D
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
t
r
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
6ns t
f
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
T
IED HIGH
OR LOW
OUTPUT
DISABLE
V
CC
FOR t
PLZ
AND t
PZL
GND FOR t
PHZ
AND t
PZ
H
OUTPUT
R
L
= 1kΩ
C
L
50pF
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
5962-8974201RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD54HC374F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD54HC574F ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD54HC574F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD54HCT374F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD54HCT574F ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD54HCT574F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
CD74HC374E ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC374M ACTIVE SOIC DW 20 25 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HC374M96 ACTIVE SOIC DW 20 2000 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HC574E ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC574M ACTIVE SOIC DW 20 25 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HC574M96 ACTIVE SOIC DW 20 2000 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT374E ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HCT374M ACTIVE SOIC DW 20 25 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT374M96 ACTIVE SOIC DW 20 2000 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT574E ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HCT574M ACTIVE SOIC DW 20 25 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT574M96 ACTIVE SOIC DW 20 2000 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT574PWR ACTIVE TSSOP PW 20 2000 Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
Addendum-Page 1
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