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CD54HC374F3A

Part # CD54HC374F3A
Description Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
Data sheet acquired from Harris Semiconductor
SCHS183C
Features
Buffered Inputs
Common Three-State Output Enable Control
Three-State Outputs
Bus Line Driving Capability
Typical Propagation Delay (Clock to Q) = 15ns at
V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2-V to 6-V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1µA at V
OL
, V
OH
Description
The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type
flip-flops with 3-state outputs and the capability to drive 15
LSTTL loads. The eight edge-triggered flip-flops enter data into
their registers on the LOW to HIGH transition of clock (CP). The
output enable (
OE) controls the 3-state outputs and is
independent of the register operation. When
OE is HIGH, the
outputs are in the high-impedance state. The 374 and 574 are
identical in function and differ only in their pinout arrangements.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC374F3A -55 to 125 20 Ld CERDIP
CD54HC574F3A -55 to 125 20 Ld CERDIP
CD54HCT374F3A -55 to 125 20 Ld CERDIP
CD54HCT574F3A -55 to 125 20 Ld CERDIP
CD74HC374E -55 to 125 20 Ld PDIP
CD74HC374M -55 to 125 20 Ld SOIC
CD74HC374M96 -55 to 125 20 Ld SOIC
CD74HC574E -55 to 125 20 Ld PDIP
CD74HC574M -55 to 125 20 Ld SOIC
CD74HC574M96 -55 to 125 20 Ld SOIC
CD74HCT374E -55 to 125 20 Ld PDIP
CD74HCT374M -55 to 125 20 Ld SOIC
CD74HCT374M96 -55 to 125 20 Ld SOIC
CD74HCT574E -55 to 125 20 Ld PDIP
CD74HCT574M -55 to 125 20 Ld SOIC
CD74HCT574M96 -55 to 125 20 Ld SOIC
CD74HCT574PWR -55 to 125 20 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel.
February 1998 - Revised May 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
CD54/74HC374, CD54/74HCT374,
CD54/74HC574, CD54/74HCT574
High-Speed CMOS Logic Octal D-Type Flip-Flop,
3-State Positive-Edge Triggered
[ /Title
(CD74
HC374
,
C
D74
HCT37
4,
CD74
HC574
,
C
D74
HCT57
2
Functional Diagram
Pinouts
CD54HC374, CD54HCT374
(CERDIP)
CD74HC374, CD74HCT374
(PDIP, SOIC)
TOP VIEW
CD54HC574, CD54HCT574
(CERDIP)
CD74HC574
(PDIP, SOIC)
CD74HCT574
(PDIP, SOIC, TSSOP)
TOP VIEW
TRUTH TABLE
INPUTS OUTPUT
OE CP Dn Qn
L HH
L LL
LLXQ0
HXXZ
H = High Level (Steady State)
L = Low Level (Steady State)
X= Don’t Care
= Transition from Low to High Level
Q0= The level of Q before the indicated steady-state input
conditions were established
Z = High Impedance State
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
V
CC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
CP
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
V
CC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
CP
Q
0
D
0
CP
OE
Q
1
D
1
Q
2
D
2
Q
3
D
3
Q
4
D
4
Q
5
D
5
Q
6
D
6
Q
7
D
7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . . θ
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - - V
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - - V
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
V
CC
or
GND
-6--±0.1 - ±1-±1 µA
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
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