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CD54HC244F

Part # CD54HC244F
Description OCTAL BUFFER/LINE DRIVER - Rail/Tube
Category IC
Availability In Stock
Qty 1
Qty Price
1 + $3.62964
Manufacturer Available Qty
RCA
Date Code: 8615
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
Data sheet acquired from Harris Semiconductor
SCHS167E
Features
• HC/HCT240 Inverting
• HC/HCT241 Non-Inverting
• HC/HCT244 Non-Inverting
• Typical Propagation Delay = 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C for HC240
• Three-State Outputs
• Buffered Inputs
• High-Current Bus Driver Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC240 and ’HCT240 are inverting three-state buffers
having two active-low output enables. The CD74HC241,
’HCT241, ’HC244 and ’HCT244 are non-inverting three-
state buffers that differ only in that the 241 has one active-
high and one active-low output enable, and the 244 has two
active-low output enables. All three types have identical
pinouts.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC240F3A -55 to 125 20 Ld CERDIP
CD54HC244F3A -55 to 125 20 Ld CERDIP
CD54HCT240F3A -55 to 125 20 Ld CERDIP
CD54HCT241F3A -55 to 125 20 Ld CERDIP
CD54HCT244F3A -55 to 125 20 Ld CERDIP
CD74HC240E -55 to 125 20 Ld PDIP
CD74HC240M -55 to 125 20 Ld SOIC
CD74HC240M96 -55 to 125 20 Ld SOIC
CD74HC241E -55 to 125 20 Ld PDIP
CD74HC241M -55 to 125 20 Ld SOIC
CD74HC241M96 -55 to 125 20 Ld SOIC
CD74HC244E -55 to 125 20 Ld PDIP
CD74HC244M -55 to 125 20 Ld SOIC
CD74HC244M96 -55 to 125 20 Ld SOIC
CD74HCT240E -55 to 125 20 Ld PDIP
CD74HCT240M -55 to 125 20 Ld SOIC
CD74HCT240M96 -55 to 125 20 Ld SOIC
CD74HCT240PW -55 to 125 20 Ld TSSOP
CD74HCT240PWR -55 to 125 20 Ld TSSOP
CD74HCT240PWT -55 to 125 20 Ld TSSOP
CD74HCT241E -55 to 125 20 Ld PDIP
CD74HCT241M -55 to 125 20 Ld SOIC
CD74HCT241M96 -55 to 125 20 Ld SOIC
CD74HCT244E -55 to 125 20 Ld PDIP
CD74HCT244M -55 to 125 20 Ld SOIC
CD74HCT244M96 -55 to 125 20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
November 1997 - Revised October 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
CD54/74HC240, CD54/74HCT240,
CD74HC241, CD54/74HCT241,
CD54/74HC244, CD54/74HCT244
High-Speed CMOS Logic
Octal Buffer/Line Drivers, Three-State
[ /Title
(CD74
HC240
,
C
D74
HCT24
0,
CD74
HC241
,
C
D74
HCT24
1,
CD74
HC244
,
C
D74
2
Pinout
CD54HC240, CD54HCT240, CD54HCT241,
CD54HC244, CD54HCT244
(CERDIP)
CD74HC240, CD74HC241, CD74HCT241,
CD74HC244, CD74HCT244
(PDIP, SOIC)
CD74HCT240,
(PDIP, SOIC, TSSOP)
TOP VIEW
Functional Diagram
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
1OE
1A0
2Y3
1A1
2Y2
1A2
1A3
2Y1
2Y0
GND
V
CC
1Y0
2A3
1Y1
2OE (241)
2A2
1Y2
2A1
1Y3
2A0
241
244 240
V
CC
1Y0
2A3
1Y1
2OE (240, 244
)
2A2
1Y2
2A1
1Y3
2A0
1OE
1A0
2Y3
1A1
2Y2
1A2
1A3
2Y1
2Y0
GND
241
244240
18
16
14
12
7
3
5
9
2
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2OE
1OE
1
19
6
2OE
1OE
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
240
241
17
4
8
11
13
15
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
240
AND
244
241
AND
244
V
CC
= 20
GND = 10
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θ
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 69
o
C/W
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . 58
o
C/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . 83
o
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance wIth JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
V
CC
or
GND
-6--±0.1 - ±1-±1 µA
Quiescent Device
Current
I
CC
V
CC
or
GND
0 6 - - 8 - 80 - 160 µA
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
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