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CC1000-RTB1

Part # CC1000-RTB1
Description RF Transceiver FSK 3V 28-PinTSSOP Tube - Rail/Tube
Category IC
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

CC1000
SWRS048A Page 13 of 55
9. 3-wire Serial Configuration Interface
CC1000
is configured via a simple 3-wire
interface (PDATA, PCLK and PALE).
There are 28 8-bit configuration registers,
each addressed by a 7-bit address. A
Read/Write bit initiates a read or write
operation. A full configuration of
CC1000
requires sending 22 data frames of 16 bits
each (7 address bits, R/W bit and 8 data
bits). The time needed for a full
configuration depend on the PCLK
frequency. With a PCLK frequency of 10
MHz the full configuration is done in less
than 46 µs. Setting the device in power
down mode requires sending one frame
only and will in this case take less than 2
µs. All registers are also readable.
In each write-cycle 16 bits are sent on the
PDATA-line. The seven most significant
bits of each data frame (A6:0) are the
address-bits. A6 is the MSB (Most
Significant Bit) of the address and is sent
as the first bit. The next bit is the R/W bit
(high for write, low for read). During
address and R/W bit transfer the PALE
(Program Address Latch Enable) must be
kept low. The 8 data-bits are then
transferred (D7:0). See Figure 4.
The timing for the programming is also
shown in Figure 4 with reference to Table
2. The clocking of the data on PDATA is
done on the negative edge of PCLK.
When the last bit, D0, of the 8 data-bits
has been loaded, the data word is loaded
in the internal configuration register.
The configuration data is stored in internal
RAM. The data is retained during power-
down mode, but not when the power-
supply is turned off. The registers can be
programmed in any order.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The seven address
bits are sent first, then the R/W bit set low
to initiate the data read-back.
CC1000
then
returns the data from the addressed
register. PDATA is in this case used as an
output and must be tri-stated (or set high n
the case of an open collector pin) by the
microcontroller during the data read-back
(D7:0). The read operation is illustrated in
Figure 5.
Figure 4. Configuration registers write operation
PCLK
PDATA
PALE
Address Write mode
6543210
7 6 5 4 3 2 1 0
Data byte
T
HD
T
SA
T
CH,min
T
CL,min
T
HA
W
T
SD
T
SA
CC1000
SWRS048A Page 14 of 55
Figure 5. Configuration registers read operation
Parameter Symbol
Min Max Units Conditions
PCLK, clock
frequency
F
CLOCK
- 10 MHz
PCLK low
pulse
duration
T
CL,min
50 ns The minimum time PCLK must be low.
PCLK high
pulse
duration
T
CH,min
50 ns The minimum time PCLK must be high.
PALE setup
time
T
SA
10 - ns The minimum time PALE must be low before
negative edge of PCLK.
PALE hold
time
T
HA
10 - ns The minimum time PALE must be held low after
the positive edge of PCLK.
PDATA setup
time
T
SD
10 - ns The minimum time data on PDATA must be ready
before the negative edge of PCLK.
PDATA hold
time
T
HD
10 - ns The minimum time data must be held at PDATA,
after the negative edge of PCLK.
Rise time T
rise
100 ns The maximum rise time for PCLK and PALE
Fall time T
fall
100 ns The maximum fall time for PCLK and PALE
Note: The set-up- and hold-times refer to 50% of VDD.
Table 2. Serial interface, timing specification
PCLK
Address Read mode
6543210
R 7 6 5 4 3 2 1 0
Data byte
PALE
PDATA
CC1000
SWRS048A Page 15 of 55
10. Microcontroller Interface
Used in a typical system,
CC1000
will
interface to a microcontroller. This
microcontroller must be able to:
Program
CC1000
into different modes
via the 3-wire serial configuration
interface (PDATA, PCLK and PALE).
Interface to the bi-directional
synchronous data signal interface
(DIO and DCLK).
Optionally the microcontroller can do
data encoding / decoding.
Optionally the microcontroller can
monitor the frequency lock status from
pin CHP_OUT (LOCK).
Optionally the microcontroller can
monitor the RSSI output for signal
strength acquisition.
10.1 Connecting the microcontroller
The microcontroller uses 3 output pins for
the configuration interface (PDATA, PCLK
and PALE). PDATA should be a bi-
directional pin for data read-back. A bi-
directional pin is used for data (DIO) to be
transmitted and data received. DCLK
providing the data timing should be
connected to a microcontroller input.
Optionally another pin can be used to
monitor the LOCK signal (available at the
CHP_OUT pin). This signal is logic level
high when the PLL is in lock. See Figure
6.
Also the RSSI signal can be connected to
the microcontroller if it has an analogue
ADC input.
The microcontroller pins connected to
PDATA and PCLK can be used for other
purposes when the configuration interface
is not used. PDATA and PCLK are high
impedance inputs as long as PALE is
high.
PALE has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull-
up. The pin state in power down mode is
summarized in Table 3.
Pin Pin state Note
PDATA Input Should be driven high or low
PCLK Input Should be driven high or low
PALE Input with internal pull-
up resistor
Should be driven high or high-impedance to minimize
power consumption
DIO Input Should be driven high or low
DCLK High-impedance
output
Table 3. CC1000 pins in power-down mode
CC1000
PDATA
PCLK
PALE
DIO
CHP_OUT
(LOCK)
Micro-
controller
DCLK
(Optional)
RSSI/IF
(Optional)
ADC
Figure 6. Microcontroller interface
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