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CC1000-RTB1

Part # CC1000-RTB1
Description RF Transceiver FSK 3V 28-PinTSSOP Tube - Rail/Tube
Category IC
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

CC1000
SWRS048A Page 7 of 55
Parameter
Min. Typ. Max. Unit Condition / Note
Current Consumption,
receive mode 433/868 MHz
7.4/9.6 mA Current is programmable and can
be increased for improved
sensitivity
Current Consumption,
average in receive mode using
polling 433/868 MHz
74/96
µA
Polling controlled by micro-
controller using 1:100 receive to
power down ratio
Current Consumption,
transmit mode 433/868 MHz:
P=0.01mW (-20 dBm)
P=0.3 mW (-5 dBm)
P=1 mW (0 dBm)
P=3 mW (5 dBm)
P=10 mW (10 dBm)
5.3/8.6
8.9/13.8
10.4/16.5
14.8/25.4
26.7/NA
mA
mA
mA
mA
mA
The ouput power is delivered to a
50 load, see also p. 32
Current Consumption, crystal osc.
Current Consumption, crystal osc.
And bias
Current Consumption, crystal osc.,
bias and synthesiser, RX/TX
30
80
105
860
4/5
5/6
µA
µA
µA
µA
mA
mA
3-8 MHz, 16 pF load
9-14 MHz, 12 pF load
14-16 MHz, 16 pF load
< 500 MHz
> 500 MHz
CC1000
SWRS048A Page 8 of 55
4. Pin Assignment
Pin no. UltraCSP
pin no.
Pin name Pin type Description
1 G3 AVDD Power (A) Power supply (3 V) for analog modules (mixer and IF)
2 F2 AGND Ground (A) Ground connection (0 V) for analog modules (mixer and IF)
3 G2 RF_IN RF Input RF signal input from antenna
4 G1 RF_OUT RF output RF signal output to antenna
5 F1 AVDD Power (A) Power supply (3 V) for analog modules (LNA and PA)
6 E2 AGND Ground (A) Ground connection (0 V) for analog modules (LNA and PA)
7 E1 AGND Ground (A) Ground connection (0 V) for analog modules (PA)
8 D1 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler)
9 C1 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler)
10 B1 L1 Analog input Connection no 1 for external VCO tank inductor
11 A1 L2 Analog input Connection no 2 for external VCO tank inductor
12 B2 CHP_OUT
(LOCK)
Analog output Charge pump current output
The pin can also be used as PLL Lock indicator. Output is high
when PLL is in lock.
13 C2 R_BIAS Analog output
Connection for external precision bias resistor (82 k, ± 1%)
14 F3 AGND Ground (A) Ground connection (0 V) for analog modules (backplane)
15 A2 AVDD Power (A) Power supply (3 V) for analog modules (general)
16 B3 AGND Ground (A) Ground connection (0 V) for analog modules (general)
17 A3 XOSC_Q2 Analog output Crystal, pin 2
18 A4 XOSC_Q1 Analog input Crystal, pin 1, or external clock input
19 B4 AGND Ground (A) Ground connection (0 V) for analog modules (guard)
20 C3 DGND Ground (D) Ground connection (0 V) for digital modules (substrate)
21 C4 DVDD Power (D) Power supply (3 V) for digital modules
22 D4 DGND Ground (D) Ground connection (0 V) for digital modules
23 E4 DIO Digital
input/output
Data input/output. Data input in transmit mode. Data output in
receive mode
24 F4 DCLK Digital output Data clock for data in both receive and transmit mode
25 G4 PCLK Digital input Programming clock for 3-wire bus
26 D3 PDATA Digital
input/output
Programming data for 3-wire bus. Programming data input for
write operation, programming data output for read operation
27 D2 PALE Digital input Programming address latch enable for 3-wire bus. Internal pull-up.
28 E3 RSSI/IF Analog output The pin can be used as RSSI or 10.7 MHz IF output to optional
external IF and demodulator. If not used, the pin should be left
open (not connected).
A=Analog, D=Digital
(Top View)
1
14 15
AVDD
AGND
RF_IN
RF_OUT
AVDD
AGND
AGND
AGND
AVDD
L1
L2
R_BIAS
CHP_OUT
AGND
CC1000
2
3
4
6
5
7
8
9
11
12
13
10
28
RSSI/IF
PALE
PDATA
PCLK
DCLK
DIO
DGND
DVDD
DGND
AGND
XOSC_Q1
AGND
XOSC_Q2
AVDD
27
26
25
23
24
22
21
20
18
17
16
19
1
14 15
AVDD
AGND
RF_IN
RF_OUT
AVDD
AGND
AGND
AGND
AVDD
L1
L2
R_BIAS
CHP_OUT
AGND
CC1000
2
3
4
6
5
7
8
9
11
12
13
10
28
RSSI/IF
PALE
PDATA
PCLK
DCLK
DIO
DGND
DVDD
DGND
AGND
XOSC_Q1
AGND
XOSC_Q2
AVDD
RSSI/IF
PALE
PDATA
PCLK
DCLK
DIO
DGND
DVDD
DGND
AGND
XOSC_Q1
AGND
XOSC_Q2
AVDD
27
26
25
23
24
22
21
20
18
17
16
19
CC1000
SWRS048A Page 9 of 55
5. Circuit Description
Figure 1. Simplified block diagram of the
CC1000
A simplified block diagram of
CC1000
is
shown in Figure 1. Only signal pins are
shown.
In receive mode
CC1000
is configured as a
traditional superheterodyne receiver. The
RF input signal is amplified by the low-
noise amplifier (LNA) and converted down
to the intermediate frequency (IF) by the
mixer (MIXER). In the intermediate
frequency stage (IF STAGE) this
downconverted signal is amplified and
filtered before being fed to the
demodulator (DEMOD). As an option a
RSSI signal, or the IF signal after the
mixer is available at the RSSI/IF pin. After
demodulation
CC1000
outputs the digital
demodulated data on the pin DIO.
Synchronisation is done on-chip providing
data clock at DCLK.
In transmit mode the voltage controlled
oscillator (VCO) output signal is fed
directly to the power amplifier (PA). The
RF output is frequency shift keyed (FSK)
by the digital bit stream fed to the pin DIO.
The internal T/R switch circuitry makes the
antenna interface and matching very easy.
The frequency synthesiser generates the
local oscillator signal which is fed to the
MIXER in receive mode and to the PA in
transmit mode. The frequency synthesiser
consists of a crystal oscillator (XOSC),
phase detector (PD), charge pump
(CHARGE PUMP), VCO, and frequency
dividers (/R and /N). An external crystal
must be connected to XOSC, and only an
external inductor is required for the VCO.
The 3-wire digital serial interface
(CONTROL) is used for configuration.
PDATA, PCLK, PALE
LNA
PA
DEMOD
VCO
PD OSC
~
/N
MIXER
CHARGE
PUMP
L1
RF_IN
DIO
CHP_OUT
IF STAGE
RF_OUT
RSSI/IF
3
CONTROL
XOSC_Q2
XOSC_Q1
/R
DCLK
L2
LPF
BIAS
R_BIAS
PDATA, PCLK, PALE
LNA
PA
DEMOD
VCO
PD OSC
~
/N
MIXER
CHARGE
PUMP
L1
RF_IN
DIO
CHP_OUT
IF STAGE
RF_OUT
RSSI/IF
3
CONTROL
XOSC_Q2
XOSC_Q1
/R
DCLK
L2
LPF
BIAS
R_BIAS
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