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CC1000-RTB1

Part # CC1000-RTB1
Description RF Transceiver FSK 3V 28-PinTSSOP Tube - Rail/Tube
Category IC
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

CC1000
SWRS048A Page 4 of 55
1. Absolute Maximum Ratings
Parameter Min. Max. Units Condition
Supply voltage, VDD -0.3 5.0 V
Voltage on any pin -0.3 VDD+0.3,
max 5.0
V
Input RF level 10 dBm
Storage temperature range
(TSSOP)
-50 150
°C
Shelf life (UltraCSP™) 1 year Room temperature and oxygen
free cabinet
Reflow soldering temperature
(TSSOP)
260
°C
IPC/JEDEC J-STD-020C
Peak reflow soldering temperature
(UltraCSP™)
255
°C
IPC/JEDEC J-STD-020C
Under no circumstances the absolute
maximum ratings given above should be
violated. Stress exceeding one or more of
the limiting values may cause permanent
damage to the device.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
2. Operating Conditions
Parameter
Min. Typ. Max. Unit Condition / Note
RF Frequency Range 300
1000 MHz Programmable in steps of 250 Hz
Operating ambient temperature range -40 85
°C
Supply voltage
2.1 3.0 3.6 V
Note: The same supply voltage
should be used for digital (DVDD)
and analogue (AVDD) power.
3. Electrical Specifications
Tc = 25°C, VDD = 3.0 V if nothing else stated
Parameter
Min. Typ. Max. Unit Condition / Note
Transmit Section
Transmit data rate
0.6 76.8 kBaud NRZ or Manchester encoding.
76.8 kBaud equals 76.8 kbit/s
using NRZ coding. See page 16.
Binary FSK frequency separation
0 65 kHz
The frequency separation is
programmable in 250 Hz steps.
65 kHz is the maximum
guaranteed separation at 1 MHz
reference frequency. Larger
separations can be achieved at
higher reference frequencies.
CC1000
SWRS048A Page 5 of 55
Parameter
Min. Typ. Max. Unit Condition / Note
Output power
433 MHz
868 MHz
-20
-20
10
5
dBm
dBm
Delivered to 50 load.
The output power is
programmable.
RF output impedance
433/868 MHz
140 / 80
Transmit mode. For matching
details see “Input/ output
matching” p.31.
Harmonics
-20 dBc An external LC or SAW filter
should be used to reduce
harmonics emission to comply
with SRD requirements. See
p.36.
Receive Section
Receiver Sensitivity, 433 MHz
Optimum sensitivity (9.3 mA)
Low current consumption (7.4 mA)
Receiver Sensitivity, 868 MHz
Optimum sensitivity (11.8 mA)
Low current consumption (9.6 mA)
-110
-109
-107
-105
dBm
dBm
dBm
dBm
2.4 kBaud, Manchester coded
data, 64 kHz frequency
separation, BER = 10
-3
See Table 6 and Table 7 page 22
for typical sensitivity figures at
other data rates.
System noise bandwidth 30 kHz 2.4 kBaud, Manchester coded
data
Cascaded noise figure
433/868 MHz
12/13 dB
Saturation
10 dBm 2.4 kBaud, Manchester coded
data, BER = 10
-3
Input IP3
-18 dBm From LNA to IF output
Blocking
40 dBc At +/- 1 MHz
LO leakage -57 dBm
Input impedance
88-j26
70-j26
52-j7
52-j4
Receive mode, series equivalent
at 315 MHz
at 433 MHz
at 868 MHz.
At 915 MHz
For matching details see “Input/
output matching” p. 31.
Turn on time 11 128 Baud The turn-on time is determined by
the demodulator settling time,
which is programmable. See p.
19
IF Section
Intermediate frequency (IF)
150
10.7
kHz
MHz
Internal IF filter
External IF filter
IF bandwidth
175 kHz
RSSI dynamic range
-105 -50 dBm
RSSI accuracy
± 6
dB
See p.33 for details
RSSI linearity
± 2
dB
CC1000
SWRS048A Page 6 of 55
Parameter
Min. Typ. Max. Unit Condition / Note
Frequency Synthesiser
Section
Crystal Oscillator Frequency
3 16 MHz Crystal frequency can be 3-4, 6-8
or 9-16 MHz. Recommended
frequencies are 3.6864, 7.3728,
11.0592 and 14.7456. See page
35 for details.
Crystal frequency accuracy
requirement
± 50
± 25
ppm 433 MHz
868 MHz
The crystal frequency accuracy
and drift (ageing and
temperature dependency) will
determine the frequency accuracy
of the transmitted signal.
Crystal operation
Parallel
C171 and C181 are loading
capacitors, see page 35
Crystal load capacitance
12
12
12
22
16
16
30
30
16
pF
pF
pF
3-4 MHz, 22 pF recommended
6-8 MHz, 16 pF recommended
9-16 MHz, 16 pF recommended
Crystal oscillator start-up time 5
1.5
2
ms
ms
ms
3.6864 MHz, 16 pF load
7.3728 MHz, 16 pF load
16 MHz, 16 pF load
Output signal phase noise
-85 dBc/Hz At 100 kHz offset from carrier
PLL lock time (RX / TX turn time)
200
µs
Up to 1 MHz frequency step
PLL turn-on time, crystal oscillator
on in power down mode
250
µs
Crystal oscillator running
Digital Inputs/Outputs
Logic “0” input voltage
0 0.3*VDD V
Logic ”1” input voltage
0.7*VDD VDD V
Logic “0” output voltage
0
0.4 V Output current -2.5 mA,
3.0 V supply voltage
Logic “1” output voltage
2.5
VDD V Output current 2.5 mA,
3.0 V supply voltage
Logic “0” input current
NA -1
µA
Input signal equals GND
Logic “1” input current
NA 1
µA
Input signal equals VDD
DIO setup time
20 ns TX mode, minimum time DIO
must be ready before the positive
edge of DCLK
DIO hold time
10 ns TX mode, minimum time DIO
must be held after the positive
edge of DCLK
Serial interface (PCLK, PDATA and
PALE) timing specification
See Table 2 page 14
Current Consumption
Power Down mode
0.2 1
µA
Oscillator core off
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