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CAT28C512NI-15

Part # CAT28C512NI-15
Description MEMORY:NONVOLATILE-FLASH
Category IC
Availability In Stock
Qty 1
Qty Price
1 + $39.95831
Manufacturer Available Qty
CSI
Date Code: 0040
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AdvancedCAT28C512/513
4
Doc. No. 25074-00 2/98
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
OUT
ACTIVE
Byte Write (WE Controlled) L H D
IN
ACTIVE
Byte Write (CE Controlled) L H D
IN
ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAPACITANCE T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol Test Max. Units Conditions
C
I/O
(1)
Input/Output Capacitance 10 pF V
I/O
= 0V
C
IN
(1)
Input Capacitance 6 pF V
IN
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
28C512/513-12 28C512/513-15
Symbol Parameter Min. Max. Min. Max. Units
t
RC
Read Cycle Time 120 150 ns
t
CE
CE Access Time 120 150 ns
t
AA
Address Access Time 120 150 ns
t
OE
OE Access Time 50 70 ns
t
LZ
(1)
CE Low to Active Output 0 0 ns
t
OLZ
(1)
OE Low to Active Output 0 0 ns
t
HZ
(1)(2)
CE High to High-Z Output 50 50 ns
t
OHZ
(1)(2)
OE High to High-Z Output 50 50 ns
t
OH
(1)
Output Hold from Address Change 0 0 ns
A.C. CHARACTERISTICS, Read Cycle
V
CC
=5V + 10%, Unless otherwise specified
Symbol Parameter Min. Max Units
t
PUR
(1)
Power-up to Read Operation 100 µs
t
PUW
(2)
Power-up to Write Operation 5 10 ms
Power-Up Timing
Advanced
CAT28C512/513
5
Doc. No. 25074-00 2/98
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
5096 FHD F04
Figure 1. A.C. Testing Input/Output Waveform(2)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
C
L
= 100 pF
OUT
C
L
INCLUDES JIG CAPACITANCE
Figure 2. A.C. Testing Load Circuit (example)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5096 FHD F03
A.C. CHARACTERISTICS, Write Cycle
V
CC
=5V+10%, unless otherwise specified
28C512/513-12 28C512/513-15
Symbol Parameter Min. Max. Min. Max. Units
t
WC
Write Cycle Time 5 5 ms
t
AS
Address Setup Time 0 0 ns
t
AH
Address Hold Time 50 50 ns
t
CS
CE Setup Time 0 0 ns
t
CH
CE Hold Time 0 0 ns
t
CW
(3)
CE Pulse Time 100 100 ns
t
OES
OE Setup Time 0 0 ns
t
OEH
OE Hold Time 0 0 ns
t
WP
(3)
WE Pulse Width 100 100 ns
t
DS
Data Setup Time 50 50 ns
t
DH
Data Hold Time 0 0 ns
t
INIT
(1)
Write Inhibit Period After Power-up 5 10 5 10 ms
t
BLC
(1)(4)
Byte Load Cycle Time 0.1 100 0.1 100 µs
AdvancedCAT28C512/513
6
Doc. No. 25074-00 2/98
ADDRESS
CE
OE
WE
t
RC
DATA OUT DATA VALIDDATA VALID
t
CE
t
OE
t
OH
t
AA
t
OHZ
t
HZ
V
IH
HIGH-Z
t
LZ
t
OLZ
DEVICE OPERATION
Read
Data stored in the CAT28C512/513 is transferred to the
data bus when WE is held high, and both OE and CE
are held low. The data bus is set to a high impedance
state when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
OE
WE
DATA OUT
t
AS
DATA IN
DATA VALID
HIGH-Z
t
CS
t
AH
t
CH
t
WC
t
OEH
t
BLC
t
DH
t
DS
t
OES
t
WP
5096 FHD F06
28C512/513 F06
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