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CAT28C512NI-15

Part # CAT28C512NI-15
Description MEMORY:NONVOLATILE-FLASH
Category IC
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CSI
Date Code: 0040
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
Advanced
CAT28C512/513
512K-Bit CMOS PARALLEL E
2
PROM
FEATURES
Fast Read Access Times: 120/150 ns
Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
Fast Write Cycle Time:
–5ms Max
CMOS and TTL Compatible I/O
Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
End of Write Detection:
–Toggle Bit
DATADATA
DATADATA
DATA Polling
Hardware and Software Write Protection
100,000 Program/Erase Cycles
100 Year Data Retention
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel E
2
PROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin
TSOP packages.
BLOCK DIAGRAM
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A
7
–A
15
CE
OE
WE
A
0
–A
6
I/O
0
–I/O
7
I/O BUFFERS
65,536 x 8
E
2
PROM
ARRAY
128 BYTE PAGE
REGISTER
V
CC
DATA POLLING
AND
TOGGLE BIT
Doc. No. 25074-00 2/98
AdvancedCAT28C512/513
2
Doc. No. 25074-00 2/98
PIN CONFIGURATION
TSOP Package (10mm X 14mm) (T14)
PLCC Package (N)
DIP Package (P)
PIN FUNCTIONS
Pin Name Function
A
0
–A
15
Address Inputs
I/O
0
–I/O
7
Data Inputs/Outputs
CE Chip Enable
OE Output Enable
Pin Name Function
WE Write Enable
V
CC
5V Supply
V
SS
Ground
NC No Connect
PLCC Package (N)
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O
6
I/O
5
I/O
4
I/O
2
A
1
A
2
V
CC
WE
A
8
A
9
A
11
OE
A
7
A
6
A
5
A
4
A
3
A
10
I/O
7
A
12
16
15
CE
I/O
3
I/O
1
I/O
0
A
0
A
14
NC
NC
NC
NC
NC
NC
NC
A
15
NC
NC
V
SS
NC
NC
29
30
31
32
33
34
35
36
37
38
39
40
I/O
2
V
SS
I/O
6
I/O
5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A
1
A
0
I/O
0
I/O
1
OE
A
10
CE
I/O
7
A
5
A
4
A
3
A
2
5
6
7
8
1
2
3
4
A
14
A
12
A
7
A
6
A
9
A
11
28
27
26
25
V
CC
WE
A
13
A
8
A
6
A
5
A
4
A
3
5
6
7
8
A
2
A
1
A
0
NC
9
10
11
12
I/O
0
13
A
8
A
9
A
11
29
28
27
26
OE
A
10
CE
25
24
23
22
I/O
7
21
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
14 15 16 17 18 19 20
4321323130
A
7
A
12
A
15
NC
V
CC
WE
A
13
I/O
4
I/O
3
16
15
I/O
6
TOP VIEW
NC
A
14
CAT28C512
29
30
31
32
NC
NC
NC
A
15
A
6
A
5
A
4
A
3
5
6
7
8
A
2
A
1
A
0
NC
9
10
11
12
I/O
0
13
A
8
A
9
A
11
29
28
27
26
OE
A
10
CE
25
24
23
22
I/O
7
21
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
14 15 16 17 18 19 20
4321323130
A
7
A
12
NC
V
CC
WE
A
13
I/O
6
TOP VIEW
NC
A
14
A
15
CAT28C513
TSOP Package (8mmx20mm) (T)
5096 FHD F01
CAT28C512
TOP VIEW
CAT28C512
TOP VIEW
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O
6
I/O
5
I/O
4
I/O
2
A
1
A
2
V
CC
WE
A
8
A
9
A
11
OE
A
7
A
6
A
5
A
4
A
3
A
10
I/O
7
A
12
16
15
CE
I/O
3
I/O
1
I/O
0
A
0
A
14
NC
NC
NC
A
15
29
30
31
32
V
ss
Advanced
CAT28C512/513
3
Doc. No. 25074-00 2/98
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
V
CC
Current (Operating, TTL) 50 mA CE = OE = V
IL
, f=6MH
z
All I/O’s Open
I
CCC
(5)
V
CC
Current (Operating, CMOS) 25 mA CE = OE = V
ILC
, f=6MH
z
All I/O’s Open
I
SB
V
CC
Current (Standby, TTL) 3 mA CE = V
IH
, All I/O’s Open
I
SBC
(6)
V
CC
Current (Standby, CMOS) 200 µA CE = V
IHC
,
All I/O’s Open
I
LI
Input Leakage Current -10 10 µAV
IN
= GND to V
CC
I
LO
Output Leakage Current -10 10 µAV
OUT
= GND to V
CC
,
CE = V
IH
V
IH
(6)
High Level Input Voltage 2 V
CC
+0.3 V
V
IL
(5)
Low Level Input Voltage -1 0.8 V
V
OH
High Level Output Voltage 2.4 V I
OH
= –400µA
V
OL
Low Level Output Voltage 0.4 V I
OL
= 2.1mA
V
WI
Write Inhibit Voltage 3.5 V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
N
END
(1)
Endurance 10
4
or 10
5
Cycles/Byte MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention 100 Years MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up 100 mA JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILC
= –0.3V to +0.3V.
(6) V
IHC
= V
CC
–0.3V to V
CC
+0.3V.
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