Schematic Diagram

Application Information

Circuit Description

Figure 1 is a block diagram of the CA3130 Series CMOS

Operational Ampliﬁers. The input terminals may be operated

down to 0.5V below the negative supply rail, and the output

can be swung very close to either supply rail in many

applications. Consequently, the CA3130 Series circuits are

ideal for single-supply operation. Three Class A ampliﬁer

stages, having the individual gain capability and current

consumption shown in Figure 1, provide the total gain of the

CA3130. A biasing circuit provides two potentials for

common use in the ﬁrst and second stages. Terminal 8 can

be used both for phase compensation and to strobe the

output stage into quiescence. When Terminal 8 is tied to the

negative supply rail (Terminal 4) by mechanical or electrical

means, the output potential at Terminal 6 essentially rises to

the positive supply-rail potential at Terminal 7. This condition

of essentially zero current drain in the output stage under the

strobed “OFF” condition can only be achieved when the

ohmic load resistance presented to the ampliﬁer is very high

(e.g.,when the ampliﬁer output is used to drive CMOS digital

circuits in Comparator applications).

Input Stage

The circuit of the CA3130 is shown in the schematic diagram.

It consists of a differential-input stage using PMOS field-effect

transistors (Q

, Q

) working into a mirror-pair of bipolar

transistors (Q

, Q

) functioning as load resistors together

with resistors R

through R

. The mirror-pair transistors also

function as a differential-to-single-ended converter to provide

base drive to the second-stage bipolar transistor (Q

). Offset

nulling, when desired, can be effected by connecting a

100,000Ω potentiometer across Terminals 1 and 5 and the

potentiometer slider arm to Terminal 4. Cascade-connected

PMOS transistors Q

, Q

are the constant-current source for

the input stage. The biasing circuit for the constant-current

source is subsequently described. The small diodes D

1 8 4

8.3V

INPUT STAGE

1kΩ

NON-INV.

INPUT

INV.-INPUT

40kΩ

5kΩ

BIAS CIRCUIT

CURRENT SOURCE FOR

“CURRENT SOURCE

LOAD” FOR Q

AND Q

V+

OUTPUT

STAGE

V-

SECOND

STAGE

OFFSET NULL

COMPENSATION STROBING

(NOTE 5)

NOTE:

5. Diodes D

through D

provide gate-oxide protection for MOSFET input stage.

CA3130, CA3130A

through D

provide gate-oxide protection against high-voltage

transients, including static electricity during handling for Q

and Q

Second-Stage

Most of the voltage gain in the CA3130 is provided by the

second ampliﬁer stage, consisting of bipolar transistor Q

and its cascade-connected load resistance provided by

PMOS transistors Q

and Q

. The source of bias potentials

for these PMOS transistors is subsequently described. Miller

Effect compensation (roll-off) is accomplished by simply

connecting a small capacitor between Terminals 1 and 8. A

47pF capacitor provides sufﬁcient compensation for stable

unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, somewhat above 8.3V, resistor R

and zener diode Z

serve to establish a voltage of 8.3V across

the series-connected circuit, consisting of resistor R

, diodes

through D

, and PMOS transistor Q

. A tap at the junction

of resistor R

and diode D

provides a gate-bias potential of

about 4.5V for PMOS transistors Q

and Q

with respect to

Terminal 7. A potential of about 2.2V is developed across

diode-connected PMOS transistor Q

with respect to Terminal

7 to provide gate bias for PMOS transistors Q

and Q

. It

should be noted that Q

is “mirror-connected (see Note 8)” to

both Q

and Q

. Since transistors Q

are designed to

be identical, the approximately 200µA current in Q

establishes a similar current in Q

and Q

as constant current

sources for both the first and second amplifier stages,

respectively.

At total supply voltages somewhat less than 8.3V, zener

diode Z

becomes nonconductive and the potential,

developed across series-connected R

, D

-D

, and Q

varies directly with variations in supply voltage.

Consequently, the gate bias for Q

and Q

varies in

accordance with supply-voltage variations. This variation

results in deterioration of the power-supply-rejection ratio

(PSRR) at total supply voltages below 8.3V. Operation at

total supply voltages below about 4.5V results in seriously

degraded performance.

Output Stage

The output stage consists of a drain-loaded inverting

ampliﬁer using CMOS transistors operating in the Class A

mode. When operating into very high resistance loads, the

output can be swung within millivolts of either supply rail.

Because the output stage is a drain-loaded ampliﬁer, its gain

is dependent upon the load impedance. The transfer

characteristics of the output stage for a load returned to the

negative supply rail are shown in Figure 2. Typical op amp

loads are readily driven by the output stage. Because large-

signal excursions are non-linear, requiring feedback for good

waveform reproduction, transient delays may be

encountered. As a voltage follower, the ampliﬁer can achieve

0.01% accuracy levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transis-

tor-pairs in linear-circuit applications, see File Number 619, data

sheet on CA3600E “CMOS Transistor Array”.

Input Current Variation with Common Mode Input

Voltage

As shown in the Table of Electrical Specifications, the input

current for the CA3130 Series Op Amps is typically 5pA at

= 25

C when Terminals 2 and 3 are at a common-mode

potential of +7.5V with respect to negative supply Terminal 4.

Figure 3 contains data showing the variation of input current

as a function of common-mode input voltage at T

=25

815

BIAS CKT.

COMPENSATION

(WHEN REQUIRED)

≈ 5X

≈

6000X

30X

INPUT

200µA 200µA

1.35mA

8mA

0mA

V+

OUTPUT

V-

STROBE

OFFSET

NULL

CA3130

(NOTE 7)

(NOTE 5)

NOTES:

6. Total supplyvoltage (forindicated voltage gains)= 15Vwith input

terminals biased so that Terminal 6 potential is +7.5V above Ter-

minal 4.

7. Total supply voltage (for indicated voltage gains) = 15V with out-

put terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

22.5

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

17.5 2012.5 15107.52.5 50

2.5

7.5

12.5

17.5

SUPPLY VOLTAGE: V+ = 15, V- = 0V

= 25

LOAD RESISTANCE = 5kΩ

500Ω

1kΩ

2kΩ

FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF

CMOS OUTPUT STAGE

CA3130, CA3130A

These data show that circuit designers can advantageously

exploit these characteristics to design circuits which typically

require an input current of less than 1pA, provided the

common-mode input voltage does not exceed 2V. As

previously noted, the input current is essentially the result of

the leakage current through the gate-protection diodes in the

input circuit and, therefore, a function of the applied voltage.

Although the finite resistance of the glass terminal-to-case

insulator of the metal can package also contributes an

increment of leakage current, there are useful compensating

factors. Because the gate-protection network functions as if it

is connected to Terminal 4 potential, and the Metal Can case

of the CA3130 is also internally tied to Terminal 4, input

Terminal 3 is essentially “guarded” from spurious leakage

currents.

Offset Nulling

Offset-voltage nulling is usually accomplished with a

100,000Ω potentiometer connected across Terminals 1 and

5 and with the potentiometer slider arm connected to

Terminal 4. A ﬁne offset-null adjustment usually can be

effected with the slider arm positioned in the mid-point of the

potentiometer’s total range.

Input-Current Variation with Temperature

The input current of the CA3130 Series circuits is typically

5pA at 25

C. The major portion of this input current is due to

leakage current through the gate-protective diodes in the input

circuit. As with any semiconductor-junction device, including

op amps with a junction-FET input stage, the leakage current

approximately doubles for every 10

C increase in

temperature. Figure 4 provides data on the typical variation of

input bias current as a function of temperature in the CA3130.

In applications requiring the lowest practical input current

and incremental increases in current because of “warm-up”

effects, it is suggested that an appropriate heat sink be used

with the CA3130. In addition, when “sinking” or “sourcing”

signiﬁcant output current the chip temperature increases,

causing an increase in the input current. In such cases, heat-

sinking can also very markedly reduce and stabilize input

current variations.

Input Offset Voltage (V

) Variation with DC Bias

and Device Operating Life

It is well known that the characteristics of a MOSFET device

can change slightly when a DC gate-source bias potential is

applied to the device for extended time periods. The

magnitude of the change is increased at high temperatures.

Users of the CA3130 should be alert to the possible impacts

of this effect if the application of the device involves

extended operation at high temperatures with a signiﬁcant

differential DC bias voltage applied across Terminals 2 and

3. Figure 5 shows typical data pertinent to shifts in offset

voltage encountered with CA3130 devices (metal can

package) during life testing. At lower temperatures (metal

can and plastic), for example at 85

C, this change in voltage

is considerably less. In typical linear applications where the

differential voltage is small and symmetrical, these

incremental changes are of about the same magnitude as

those encountered in an operational ampliﬁer employing a

bipolar transistor input stage. The 2V

differential voltage

example represents conditions when the ampliﬁer output

stage is “toggled”, e.g., as in comparator applications.

7.5

2.5

-101234567

INPUT CURRENT (pA)

INPUT VOLTAGE (V)

= 25

CA3130

15V

-10V

V+

V-

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE

= ±7.5V

4000

1000

100

-80 -60 -40 -20 0 20 40 60 80 100 120 140

INPUT CURRENT (pA)

TEMPERATURE (

FIGURE 4. INPUT CURRENT vs TEMPERATURE

CA3130, CA3130A

Part #	CA3130E
Description	IC OPAMP GP 15MHZ 8DIP
Category	IC
Availability	Out of Stock
Qty	0

CA3130E

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