C8051F040/1/2/3/4/5/6/7
298 Rev. 1.5
23.2.4. Toggle Output Mode
Timer n have the capability to toggle the state of their respective output port pins (T2, T3, or T4) to produce
a 50% duty cycle waveform output. The port pin state will change upon the overflow or underflow of the
respective timer (depending on whether the timer is counting up or down). The toggle frequency is deter-
mined by the clock source of the timer and the values loaded into RCAPnH and RCAPnL. When counting
DOWN, the auto-reload value for the timer is 0xFFFF, and underflow will occur when the value in the timer
matches the value stored in RCAPnH:RCAPnL. When counting UP, the auto-reload value for the timer is
RCAPnH:RCAPnL, and overflow will occur when the value in the timer transitions from 0xFFFF to the
reload value.
To output a square wave, the timer is placed in reload mode (the Capture/Reload Select Bit in TMRnCN
and the Timer/Counter Select Bit in TMRnCN are cleared to ‘0’). The timer output is enabled by setting the
Timer Output Enable Bit in TMRnCF to ‘1’. The timer should be configured via the timer clock source and
reload/underflow values such that the timer overflow/underflows at 1/2 the desired output frequency. The
port pin assigned by the crossbar as the timer’s output pin should be configured as a digital output (see
Section “17. Port Input/Output” on page 203). Setting the timer’s Run Bit (TRn) to ‘1’ will start the toggle
of the pin. A Read/Write of the Timer’s Toggle Output State Bit (TMRnCF.2) is used to read the state of the
toggle output, or to force a value of the output. This is useful when it is desired to start the toggle of a pin in
a known state, or to force the pin into a desired state when the toggle mode is halted.
Equation 23.1. Square Wave Frequency
Equation 23.1 applies regardless of whether the timer is configured to count up or down.
F
sq
F
TCLK
265536RCAPn–
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=
