C8051F040/1/2/3/4/5/6/7

280 Rev. 1.5

22.2.2. 9-Bit UART

9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-

ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB81

(SCON1.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-

ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit

goes into RB81 (SCON1.2) and the stop bit is ignored.

Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit

Interrupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data

reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to ‘1’. After the stop bit

is received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met:

(1) RI1 must be logic 0, and (2) if MCE1 is logic 1, the 9th bit must be logic 1 (when MCE1 is logic 0, the

state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in

SBUF1, the ninth bit is stored in RB81, and the RI1 flag is set to ‘1’. If the above conditions are not met,

SBUF1 and RB81 will not be loaded and the RI1 flag will not be set to ‘1’. A UART1 interrupt will occur if

enabled when either TI1 or RI1 is set to ‘1’.

Figure 22.5. 9-Bit UART Timing Diagram

D1D0 D2 D3 D4 D5 D6 D7

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 281

22.3. Multiprocessor Communications

9-Bit UART mode supports multiprocessor communication between a master processor and one or more

slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or

more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte

in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.

Setting the MCE1 bit (SCON1.5) of a slave processor configures its UART such that when a stop bit is

received, the UART will generate an interrupt only if the ninth bit is logic one (RB81 = 1) signifying an

address byte has been received. In the UART interrupt handler, software should compare the received

address with the slave's own assigned 8-bit address. If the addresses match, the slave should clear its

MCE1 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed

leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes,

thereby ignoring the data. Once the entire message is received, the addressed slave should reset its

MCE1 bit to ignore all transmissions until it receives the next address byte.

Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple

slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master

processor can be configured to receive all transmissions or a protocol can be implemented such that the

master/slave role is temporarily reversed to enable half-duplex transmission between the original master

and slave(s).

Figure 22.6. UART Multi-Processor Mode Interconnect Diagram

Master

Device

Slave

Device

TXRX RX TX

Slave

Device

RX TX

Slave

Device

RX TX

+5V

C8051F040/1/2/3/4/5/6/7

282 Rev. 1.5

SFR Definition 22.1. SCON1: Serial Port 1 Control

Bit7: S1MODE: Serial Port 1 Operation Mode.

This bit selects the UART1 Operation Mode.

0: Mode 0: 8-bit UART with Variable Baud Rate

1: Mode 1: 9-bit UART with Variable Baud Rate

Bit6: UNUSED. Read = 1b. Write = don’t care.

Bit5: MCE1: Multiprocessor Communication Enable.

The function of this bit is dependent on the Serial Port 0 Operation Mode.

Mode 0: Checks for valid stop bit.

0: Logic level of stop bit is ignored.

1: RI1 will only be activated if stop bit is logic level 1.

Mode 1: Multiprocessor Communications Enable.

0: Logic level of ninth bit is ignored.

1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1.

Bit4: REN1: Receive Enable.

This bit enables/disables the UART receiver.

0: UART1 reception disabled.

1: UART1 reception enabled.

Bit3: TB81: Ninth Transmission Bit.

The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It

is not used in 8-bit UART Mode. Set or cleared by software as required.

Bit2: RB81: Ninth Receive Bit.

RB81 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th

data bit in Mode 1.

Bit1: TI1: Transmit Interrupt Flag.

Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in 8-

bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART1

interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt service

routine. This bit must be cleared manually by software.

Bit0: RI1: Receive Interrupt Flag.

Set to ‘1’ by hardware when a byte of data has been received by UART1 (set at the STOP

bit sampling time). When the UART1 interrupt is enabled, setting this bit to ‘1’ causes the

CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by

software.

R/WR/WR/WR/WR/WR/WR/W R/WReset Value

S1MODE - MCE1 REN1 TB81 RB81 TI1 RI1 01000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x98

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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