C8051F040/1/2/3/4/5/6/7

274 Rev. 1.5

SFR Definition 21.1. SCON0: UART0 Control

Bits7-6: SM00-SM10: Serial Port Operation Mode:

Write:

When written, these bits select the Serial Port Operation Mode as follows:

Reading these bits returns the current UART0 mode as defined above.

Bit5: SM20: Multiprocessor Communication Enable.

The function of this bit is dependent on the Serial Port Operation Mode.

Mode 0: No effect

Mode 1: Checks for valid stop bit.

0: Logic level of stop bit is ignored.

1: RI0 will only be activated if stop bit is logic level 1.

Mode 2 and 3: Multiprocessor Communications Enable.

0: Logic level of ninth bit is ignored.

1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1 and the

received address matches the UART0 address or the broadcast address.

Bit4: REN0: Receive Enable.

This bit enables/disables the UART0 receiver.

0: UART0 reception disabled.

1: UART0 reception enabled.

Bit3: TB80: Ninth Transmission Bit.

The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is

not used in Modes 0 and 1. Set or cleared by software as required.

Bit2: RB80: Ninth Receive Bit.

The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if

SM20 is logic 0, RB80 is assigned the logic level of the received stop bit. RB8 is not used in

Mode 0.

Bit1: TI0: Transmit Interrupt Flag.

Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in

Mode 0, or at the beginning of the stop bit in other modes). When the UART0 interrupt is

enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine.

This bit must be cleared manually by software.

Bit0: RI0: Receive Interrupt Flag.

Set by hardware when a byte of data has been received by UART0 (as selected by the

SM20 bit). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to

the UART0 interrupt service routine. This bit must be cleared manually by software.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

SM00 SM10 SM20 REN0 TB80 RB80 TI0 RI0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0x98

SM00 SM10 Mode

0 0 Mode 0: Synchronous Mode

0 1 Mode 1: 8-Bit UART, Variable Baud Rate

1 0 Mode 2: 9-Bit UART, Fixed Baud Rate

1 1 Mode 3: 9-Bit UART, Variable Baud Rate

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 275

SFR Definition 21.2. SSTA0: UART0 Status and Clock Selection

Bit7: FE0: Frame Error Flag.

This flag indicates if an invalid (low) STOP bit is detected.

0: Frame Error has not been detected

1: Frame Error has been detected.

Bit6: RXOV0: Receive Overrun Flag.

This flag indicates new data has been latched into the receive buffer before software has

read the previous byte.

0: Receive overrun has not been detected.

1: Receive Overrun has been detected.

Bit5: TXCOL0: Transmit Collision Flag.

This flag indicates user software has written to the SBUF0 register while a transmission is in

progress.

0: Transmission Collision has not been detected.

1: Transmission Collision has been detected.

Bit4: SMOD0: UART0 Baud Rate Doubler Enable.

This bit enables/disables the divide-by-two function of the UART0 baud rate logic for config-

urations described in the UART0 section.

0: UART0 baud rate divide-by-two enabled.

1: UART0 baud rate divide-by-two disabled.

Bits3-2: UART0 Transmit Baud Rate Clock Selection Bits.

Bits1-0: UART0 Receive Baud Rate Clock Selection Bits

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

FE0 RXOV0 TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0x91

S0TCLK1 S0TCLK0 Serial Transmit Baud Rate Clock Source

0 0 Timer 1 generates UART0 TX Baud Rate

0 1 Timer 2 Overflow generates UART0 TX baud rate

1 0 Timer 3 Overflow generates UART0 TX baud rate

1 1 Timer 4 Overflow generates UART0 TX baud rate

S0RCLK1 S0RCLK0 Serial Receive Baud Rate Clock Source

0 0 Timer 1 generates UART0 RX Baud Rate

0 1 Timer 2 Overflow generates UART0 RX baud rate

1 0 Timer 3 Overflow generates UART0 RX baud rate

1 1 Timer 4 Overflow generates UART0 RX baud rate

C8051F040/1/2/3/4/5/6/7

276 Rev. 1.5

SFR Definition 21.3. SBUF0: UART0 Data Buffer

SFR Definition 21.4. SADDR0: UART0 Slave Address

SFR Definition 21.5. SADEN0: UART0 Slave Address Enable

Bits7-0: SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)

This is actually two registers; a transmit and a receive buffer register. When data is moved to

SBUF0, it goes to the transmit buffer and is held for serial transmission. Moving a byte to

SBUF0 is what initiates the transmission. When data is moved from SBUF0, it comes from

the receive buffer.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0x99

Bits7-0: SADDR0.[7:0]: UART0 Slave Address

The contents of this register are used to define the UART0 slave address. Register SADEN0

is a bit mask to determine which bits of SADDR0 are checked against a received address:

corresponding bits set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0

are “don’t cares”.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xA9

Bits7-0: SADEN0.[7:0]: UART0 Slave Address Enable

Bits in this register enable corresponding bits in register SADDR0 to determine the UART0

slave address.

0: Corresponding bit in SADDR0 is a “don’t care”.

1: Corresponding bit in SADDR0 is checked against a received address.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xB9

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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Technical Document