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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 271
21.3. Configuration of a Masked Address
The UART0 address is configured via two SFRs: SADDR0 (Serial Address) and SADEN0 (Serial Address
Enable). SADEN0 sets the bit mask for the address held in SADDR0: bits set to logic 1 in SADEN0 corre-
spond to bits in SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0
correspond to “don’t care” bits in SADDR0.
Setting the SM20 bit (SCON0.5) configures UAR
T0 such that when a stop bit is received, UART0 will gen-
erate an interrupt only if the ninth bit is logic 1 (RB80 = ‘1’) and the received data byte matches the UART0
slave address. Following the received address interrupt, the slave will clear its SM20 bit to enable inter-
rupts on the reception of the following data byte(s). Once the entire message is received, the addressed
slave resets its SM20 bit to ignore all transmissions until it receives the next address byte. While SM20 is
logic 1, UART0 ignores all bytes that do not match the UART0 address and include a ninth bit that is logic
1.
21.4. Broadcast Addressing
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast
address is the logical OR of registers SADDR0 and SADEN0, and ‘0’s of the result are treated as “don’t
cares”. Typically a broadcast address of 0xFF (hexadecimal) is acknowledged by all slaves, assuming
“don’t care” bits as ‘1’s. The master processor can be configured to receive all transmissions or a protocol
can be implemented such that the master/slave role is temporarily reversed to enable half-duplex trans-
mission between the original master and slave(s).
Note in the above examples 4, 5, and 6, each slave wo
uld recognize as “valid” an address of 0xFF as a
broadcast address. Also note that examples 4, 5, and 6 uses the same SADDR0 and SADEN0 register
values as shown in the examples 1, 2, and 3 respectively (slaves #1, 2, and 3). Thus, a master could
address each slave device individually using a masked address, and also broadcast to all three slave
devices. For example, if a Master were to send an address “11110101”, only slave #1 would recognize the
address as valid. If a master were to then send an address of “11111111”, all three slave devices would rec-
ognize the address as a valid broadcast address.
Example 1, SLAVE #1 Example 2, SLAVE #2 Example 3, SLAVE #3
SADDR0 = 00110101 SADDR0
=
00110101
SADDR0 = 00110101
SADEN0 = 00001111 SADEN0
=
11110011
SADEN0 = 11000000
UART0 Address = xxxx0101 UART0 Address = 0011xx01 UART0 Address = 00xxxxxx
Example 4, SLAVE #1 Example 5, SLAVE #2 Example 6, SLAVE #3
SADDR0 = 00110101 SADDR0 = 00110101 SADDR0 = 00110101
SADEN0 = 00001111 SADEN0 = 11110011 SADEN0 = 11000000
Broadcast Address = 00111111 Broadcast Address = 11110111 Broadcast Address = 11110101
Where all ZEROES in the Broadcast address are don’t cares.
C8051F040/1/2/3/4/5/6/7
272 Rev. 1.5
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram
21.5. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SSTA0) reads '1' if
user software writes data to the
SBUF0 register while a transmit is in progress.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SSTA0) reads '1
' if a new data byte is latched into the receive
buffer before software has read the previous byte. The Frame Error bit (FE0 in register SSTA0) reads '1' if
an invalid (low) STOP bit is detected.
Master
Device
Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
+5V
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 273
Table 21.2. Oscillator Frequencies for Standard Baud Rates
Oscillator frequency
(MHz)
Divide Factor
Timer 1 Reload
Va
lue
1
Timer 2, 3, or 4
Reload Value
Resulting Baud Rate (Hz)
2
24.0 208 0xF3 0xFFF3 115200 (115384)
22.1184 192 0xF4 0xFFF4 115200
18.432 160 0xF6 0xFFF6 115200
11.0592 96 0xFA 0xFFFA 115200
3.6864 32 0xFE 0xFFFE 115200
1.8432 16 0xFF 0xFFFF 115200
24.0 832 0xCC 0xFFCC 28800 (28846)
22.1184 768 0xD0 0xFFD0 28800
18.432 640 0xD8 0xFFD8 28800
11.0592 348 0xE8 0xFFE8 28800
3.6864 128 0xF8 0xFFF8 28800
1.8432 64 0xFC 0xFFFC 28800
24.0 2496 0x64 0xFF64 9600 (9615)
22.1184 2304 0x70 0xFF70 9600
18.432 1920 0x88 0xFF88 9600
11.0592 1152 0xB8 0xFFB8 9600
3.6864 384 0xE8 0xFFE8 9600
1.8432 192 0xF4 0xFFF4 9600
Notes:
1. Assumes SMOD0=1 and T1M=1.
2. Nu
mbers in parenthesis show the actual baud rate.
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