C8051F040/1/2/3/4/5/6/7
Rev. 1.5 267
Figure 21.3. UART0 Mode 0 Interconnect
21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 provides standard asynchronous, full-duplex communication using a total of 10 bits per data byte:
one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and
received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into
RB80 (SCON0.2).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop
bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are
met: RI0 must be logic 0, and if SM20 is logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 are set.
Figure 21.4. UART0 Mode 1 Timing Diagram
The baud rate generated in Mode 1 is a function of timer overflow, shown in Equation 21.1 and
Equation 21.3. UART0 can use Timer 1 operating in 8-Bit Auto-Reload Mode, or Timer 2, 3, or 4 operating
in Auto-reload Mode to generate the baud rate (note that the TX and RX clocks are selected separately).
On each timer overflow event (a rollover from all ones—0xFF for Timer 1, 0xFFFF for Timers 2, 3 and 4—
to zero) a clock is sent to the baud rate logic.
Timers 1, 2, 3, and 4 are selected as the baud rate source with bits in the SSTA0 register (see SFR Defini-
tion 21.2). The transmit baud rate clock is selected using the S0TCLK1 and S0TCLK0 bits, and the receive
baud rate clock is selected using the S0RCLK1 and S0RCLK0 bits.
The Mode 1 baud rate equations are shown below, where T1M is bit4 of register CKCON, TH1 is the 8-bit
reload register for Timer 1, and [RCAPnH, RCAPnL] is the 16-bit reload register for Timer 2, 3, or 4.
Equation 21.1. Mode 1 Baud Rate using Timer 1
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK is selected as described in Section “23.1. Timer 0 and Timer 1” on page 287. The
Timer 1 overflow rate is calculated as shown in Equation 21.2.
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK
STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE
Mode1_BaudRate 1 32 Timer1_OverflowRate=
When SMOD0 = 0:
Mode1_BaudRate 1 16 Timer1_OverflowRate=
When SMOD0 = 1:
