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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 253
Slave Receiver
0x60 Own slave address + W received. ACK trans-
mitted.
Wait for data.
0x68 Arbitration lost in sending SLA + R/W as mas-
ter. Own address + W received. ACK transmit-
ted.
Save current data for retry when bus is
free
. Wait for data.
0x70 General call address received. ACK transmit-
ted.
Wait for data.
0x78 Arbitration lost in sending SLA + R/W as mas-
ter. General call address received. ACK trans-
mitted.
Save current data for retry when bus is
free
.
0x80 Data byte received. ACK transmitted. Read SMB0DAT. Wait for next byte or
STOP.
0x88 Data byte received. NACK transmitted. Set STO to reset SMBus.
0x90 Data byte received after general call address.
ACK transmitted.
Read SMB0DAT. Wait for next byte or
STOP.
0x98 Data byte received after general call address.
NACK transmitted.
Set STO to reset SMBus.
0xA0 STOP or repeated START received.
No action necessary.
Slave Transmitter
0xA8 Own address + R received. ACK transmitted. Load SMB0DAT with data to transmit.
0xB0 Arbitration lost in transmitting SLA + R/W as
ma
ster. Own address + R received. ACK
transmitted.
Save current data for retry when bus is
free. Load SMB0DAT with data to trans-
mit.
0xB8 Data byte transmitted. ACK
received. Load SMB0DAT with data to transmit.
0xC0 Data byte transmitted. NACK received. Wait for STOP.
0xC8 Last data byte transmitted (AA=0). ACK
r
eceived.
Set STO to reset SMBus.
Slave
0xD0 SCL Clock High Timer per SMB0CR timed out Set STO to reset SMBus.
All
0x00 Bus Error (illegal START or STOP) Set STO to reset SMBus.
0xF8 Idle State does not set SI.
Table 19.1. SMB0STA Status Codes and States (Continued)
Mode
Status
Code
SMBus State Typical Action
C8051F040/1/2/3/4/5/6/7
254 Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 255
20. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 20.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSMD1
NSSMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
TXBMT
SPIEN
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