C8051F040/1/2/3/4/5/6/7

250 Rev. 1.5

SFR Definition 19.4. SMB0ADR: SMBus0 Address

19.4.5. Status Register

The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 inter-

face. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most

significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at

zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight. This facilitates the use of sta-

tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code

to service the state or jump to a more extensive service routine).

For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is

logic 1. Software should never write to the SMB0STA register; doing so will yield indeterminate results. The

28 SMBus0 states, along with their corresponding status codes, are given in Table 19.1.

Bits7-1: SLV6-SLV0: SMBus0 Slave Address.

These bits are loaded with the 7-bit slave address to which SMBus0 will respond when oper-

ating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address

and corresponds to the first bit of the address byte received.

Bit0: GC: General Call Address Enable.

This bit is used to enable general call address (0x00) recognition.

0: General call address is ignored.

1: General call address is recognized.

R/WR/WR/WR/WR/WR/WR/W R/WReset Value

SLV6 SLV5 SLV4 SLV3 SLV2 SLV1 SLV0 GC 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xC3

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 251

SFR Definition 19.5. SMB0STA: SMBus0 Status

Bits7-3: STA7-STA3: SMBus0 Status Code.

These bits contain the SMBus0 Status Code. There are 28 possible status codes; each sta-

tus code corresponds to a single SMBus state. A valid status code is present in SMB0STA

when the SI flag (SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when

the SI flag is logic 0. Writing to the SMB0STA register at any time will yield indeterminate

results.

Bits2-0: STA2-STA0: The three least significant bits of SMB0STA are always read as logic 0 when

the SI flag is logic 1.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

STA7 STA6 STA5 STA4 STA3 STA2 STA1 STA0 11111000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xC1

C8051F040/1/2/3/4/5/6/7

252 Rev. 1.5

Table 19.1. SMB0STA Status Codes and States

Mode

Status

Code

SMBus State Typical Action

MT/

0x08 START condition transmitted. Load SMB0DAT with Slave Address +

R/W. Clear STA.

0x10 Repeated START condition transmitted. Load SMB0DAT with Slave Address +

R/W. Clear STA.

Master Transmitter

0x18 Slave Address + W transmitted. ACK

received.

Load SMB0DAT with data to be transmit-

ted.

0x20 Slave Address + W transmitted. NACK

eceived.

Acknowledge poll to retry. Set STO +

STA.

0x28 Data byte transmitted. ACK

received.

1) Load SMB0DAT with next byte, OR

2) Set STO, OR

3) Clear STO then set STA for repeated

START.

0x30 Data byte transmitted. NACK received. 1) Retry transfer OR

2) Set STO.

0x38 Arbitration Lost.

Save current data.

Master Receiver

0x40 Slave Address + R transmitted. ACK received. If only receiving one byte, clear AA (send

NACK after received byte). Wait for

received data.

0x48 Slave Address + R transmitted. NACK

eceived.

Acknowledge poll to retry. Set STO +

STA.

0x50 Data byte received. ACK transmitted. Read SMB0DAT. Wait for next byte. If

byte is last byte, clear AA.

0x58 Data byte received. NACK transmitted. Set STO.

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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