C8051F040/1/2/3/4/5/6/7

Rev. 1.5 247

SFR Definition 19.1. SMB0CN: SMBus0 Control

Bit7: BUSY: Busy Status Flag.

0: SMBus0 is free

1: SMBus0 is busy

Bit6: ENSMB: SMBus Enable.

This bit enables/disables the SMBus serial interface.

0: SMBus0 disabled.

1: SMBus0 enabled.

Bit5: STA: SMBus Start Flag.

0: No START condition is transmitted.

1: When operating as a master, a START condition is transmitted if the bus is free. (If the

bus is not free, the START is transmitted after a STOP is received.) If STA is set after one or

more bytes have been transmitted or received and before a STOP is received, a repeated

START condition is transmitted.

Bit4: STO: SMBus Stop Flag.

0: No STOP condition is transmitted.

1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP condi-

tion is received, hardware clears STO to logic 0. If both STA and STO are set, a STOP con-

dition is transmitted followed by a START condition. In slave mode, setting the STO flag

causes SMBus to behave as if a STOP condition was received.

Bit3: SI: SMBus Serial Interrupt Flag.

This bit is set by hardware when one of 27 possible SMBus0 states is entered. (Status code

0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes

the CPU to vector to the SMBus interrupt service routine. This bit is not automatically

cleared by hardware and must be cleared by software.

Bit2: AA: SMBus Assert Acknowledge Flag.

This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL

line.

0: A "not acknowledge" (high level on SDA) is returned during the acknowledge cycle.

1: An "acknowledge" (low level on SDA) is returned during the acknowledge cycle.

Bit1: FTE: SMBus Free Timer Enable Bit

0: No timeout when SCL is high

1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.

Bit0: TOE: SMBus Timeout Enable Bit

0: No timeout when SCL is low.

1: Timeout when SCL low time exceeds limit specified by Timer 4, if enabled.

R R/W R/W R/W R/W R/W R/W R/W Reset Value

BUSY ENSMB STA STO SI AA FTE TOE 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xC0

C8051F040/1/2/3/4/5/6/7

248 Rev. 1.5

19.4.2. Clock Rate Register

SFR Definition 19.2. SMB0CR: SMBus0 Clock Rate

Bits7-0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset

The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master

mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The

timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.

The SMB0CR setting should be bounded by the following equation, where SMB0CR is the

unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in Hz:

The resulting SCL signal high and low times are given by the following equations:

Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the

following equation:

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xCF

SMB0CR 288 0.85– SYSCLK1.124 6E

LOW

256 SMB0CR–SYSCLK=

HIGH

258 SMB0CR–SYSCLK 625ns+

BFT

256 SMB0CR–1+

SYSCLK

-----------------------------------------------------



C8051F040/1/2/3/4/5/6/7

Rev. 1.5 249

19.4.3. Data Register

The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just

been received. Software can read or write to this register while the SI flag is set to logic 1; software should

not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag reads logic 0

since the hardware may be in the process of shifting a byte of data in or out of the register.

Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received

data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously

being shifted in. Therefore, SMB0DAT always contains the last data byte present on the bus. In the event

of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in

SMB0DAT.

SFR Definition 19.3. SMB0DAT: SMBus0 Data

19.4.4. Address Register

The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the

seven most-significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the

recognition of the general call address (0x00). If Bit0 is set to logic 1, the general call address will be recog-

nized. Otherwise, the general call address is ignored. The contents of this register are ignored when

SMBus0 is operating in master mode.

Bits7-0: SMB0DAT: SMBus0 Data.

The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial inter-

face or a byte that has just been received on the SMBus0 serial interface. The CPU can

read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set to

logic 1. When the SI flag is not set, the system may be in the process of shifting data and the

CPU should not attempt to access this register.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xC2

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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Technical Document