C8051F040/1/2/3/4/5/6/7

Rev. 1.5 25

1.1. CIP-51™ Microcontroller Core

1.1.1. Fully 8051 Compatible

The C8051F04x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-

51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers

can be used to develop software. The core has all the peripherals included with a standard 8052, including

five 16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function

1.1.2. Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-

dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system

clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-

cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than

four system clock cycles.

The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that

require each execution time.

With the CIP-51's maximum system clock at 25 MHz, it ha

s a peak throughput of 25 MIPS. Figure 1.5

shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system

clocks.

Figure 1.5. Comparison of Peak MCU Execution Speeds

Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8

Number of Instructions 26 50 5 14 7 3 1 2 1

ADuC812

8051

(16 MHz clk)

Philips

80C51

(33 MHz clk)

Microchip

PIC17C75x

(33 MHz clk)

Silicon Labs

CIP-51

(25 MHz clk)

MIPS

C8051F040/1/2/3/4/5/6/7

26 Rev. 1.5

1.1.3. Additional Features

The C8051F04x MCU family includes several key enhancements to the CIP-51 core and peripherals to

improve overall performance and ease of use in end applications.

The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the stan-

dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt

driven system requires less intervention by the MCU, giving it more effective throughput. The extra inter-

rupt sources are very useful when building multi-tasking, real-time systems.

There are up to seven reset sources for the MCU: an on-board V

monitor, a Watchdog Timer, a missing

clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input

pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the

internally generated POR to be output on the /RST pin. Each reset source except for the V

monitor and

Reset Input pin may be disabled by the user in software; the V

monitor is enabled/disabled via the

MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during

MCU initialization.

The MCU has an internal, stand alone clock generator which is used by default as the system clock after

any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a

crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can

be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter-

nal crystal source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed.

Figure 1.6. On-Board Clock and Reset

WDT

XTAL1

XTAL2

OSC

Internal

Clock

Generator

System

Clock

CIP-51

Microcontroller

Core

Missing

Clock

Detector

(one-

shot)

WDT

Strobe

Software Reset

Extended Interrupt

Handler

Clock Select

RST

Supply

Reset

Timeout

(wired-OR)

System Reset

Supply

Monitor

PRE

Reset

Funnel

CP0+

Comparator0

CP0-

(Port I/O)

Crossbar

CNVSTR

(CNVSTR

reset

enable)

(CP0

reset

enable)

WDT

Enable

MCD

Enable

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 27

1.2. On-Chip Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data

RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general

purpose RAM, and direct addressing accesses the 128 byte SFR address space. The CIP-51 SFR

address space contains up to 256 SFR Pages. In this way, the CIP-51 MCU can accommodate the many

SFRs required to control and configure the various peripherals featured on the device. The lower

128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as

four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.

The CIP-51 in the C8051F04x MCUs additionally has an on-chip 4 kB RAM block and an external memory

interface (EMIF) for accessing off-chip data memory or memory-mapped peripherals. The on-chip 4 byte

block can be addressed over the entire 64 kB external data memory address range (overlapping 4 kB

boundaries). External data memory address space can be mapped to on-chip memory only, off-chip mem-

ory only, or a combination of the two (addresses up to 4 kB directed to on-chip, above 4 kB directed to

EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines.

The MCU's program memory consists of 64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) of Flash.

This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip pro-

gramming voltage. The 512 bytes from addresses 0xFE00 to 0xFFFF are reserved for the 64 kB devices.

There is also a single 128 byte sector at address 0x10000 to 0x1007F, which may be useful as a small

table for software constants. See Figure 1.7 for the MCU system memory map.

Figure 1.7. On-Chip Memory Map

PROGRAM/DATA MEMORY

(FLASH)

(Direct and Indirect

Addressing)

0x00

0x7F

Upper 128 RAM

(Indirect Addressing

Only)

0x80

0xFF

Special Function

Registers

(Direct Addressing Only)

DATA MEMORY (RAM)

General Purpose

Registers

0x1F

0x20

0x2F

Bit Addressable

Lower 128 RAM

(Direct and Indirect

Addressing)

0x30

INTERNAL DATA ADDRESS SPACE

EXTERNAL DATA ADDRESS SPACE

XRAM - 4096 Bytes

(accessable using MOVX

instruction)

0x0000

0x0FFF

Off-chip XRAM space

0x1000

0xFFFF

64 kB

Flash

(In-System

Programmable in 512

Byte Sectors)

0x0000

RESERVED

0xFE00

0xFDFF

Scrachpad Memory

(DATA only)

0x1007F

0x10000

Up To

256 SFR Pages

C8051F040/1/2/3/4/5

32 kB

Flash

(In-System

Programmable in 512

Byte Sectors)

0x0000

RESERVED

0x8000

0x7FFF

Scrachpad Memory

(DATA only)

0x1007F

0x10000

C8051F046/7

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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