Bit 4: CANIF: CAN Interrupt Flag. Write = don’t care.
0: CAN interrupt has not occurred.
1: CAN interrupt has occurred and is active.
CANIF is controlled by the CAN controller and is cleared by hardware once all interrupt con-
ditions have been cleared in the CAN controller. See Section 3.4.1 in the Bosch CAN User’s
Guide (page 24) for more information concerning CAN controller interrupts.
*All CAN registers’ functions/definitions are listed and described in the Bosch CAN
User’s Guide with the exception of the CANIF bit.
This register may be accessed directly in the CIP-51 SFR register space, or through the indi-
rect, index method (See Section “18.2.5. Using CAN0ADR, CAN0DATH, and CANDATL to
Access CAN Registers” on page 232).
R/W R/W R/W R R/W R/W R/W R/W Reset Value
***CANIF****
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xF8
1
All CAN registers’ functions/definitions are listed and described in the Bosch CAN
User’s Guide.
This register may be accessed directly in the CIP-51 SFR register space, or through the indi-
rect, index method (See Section “18.2.5. Using CAN0ADR, CAN0DATH, and CANDATL to
Access CAN Registers” on page 232).
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Please see the Bosch CAN User’s Guide for a complete definition of this register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xDB
1
