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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
226 Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 227
18. Controller Area Network (CAN0)
IMPORTANT DOCUMENTATION NOTE: The Bosch CAN Controller is integrated in the C8051F04x Fam-
ily of devices. This section of the data sheet gives a description of the CAN controller as an overview and
offers a description of how the Silicon Labs CIP-51 MCU interfaces with the on-chip Bosch CAN controller.
In order to use the CAN controller, please refer to Bosch’s C_CAN Users Manual (revision 1.2) as an
accompanying manual to Silicon Labs’ C8051F04x Data sheet.
The C8051F04x family of devices feature a Control Area Network (CAN) controller that enables serial com-
munication using the CAN protocol. Silicon Labs CAN facilitates communication on a CAN network in
accordance with the Bosch specification 2.0A (basic CAN) and 2.0B (full CAN). The CAN controller con-
sists of a CAN Core, Message RAM (separate from the CIP-51 RAM), a message handler state machine,
and control registers. Silicon Labs CAN is a protocol controller and does not provide physical layer drivers
(i.e., transceivers). Figure 18.1 shows an example typical configuration on a CAN bus.
Silicon Labs CAN operates at bit rates of up to 1 Mbit/second, though this can be limited by the physical
layer chosen to transmit data on the CAN bus. The CAN processor has 32 Message Objects that can be
configured to transmit or receive data. Incoming data, message objects and their identifier masks are
stored in the CAN message RAM. All protocol functions for transmission of data and acceptance filtering is
performed by the CAN controller and not by the CIP-51 MCU. In this way, minimal CPU bandwidth is
needed to use CAN communication. The CIP-51 configures the CAN controller, accesses received data,
and passes data for transmission via Special Function Registers (SFRs) in the CIP-51.
Figure 18.1. Typical CAN Bus Configuration
C8051F04x
CANTX
CANRX
CAN_H
CAN_L
Isolation/Buffer (Optional)
CAN
Transceiver
Isolation/Buffer (Optional)
CAN
Transceiver
Isolation/Buffer (Optional)
CAN
Transceiver
R
R
CAN Protocol Device CAN Protocol Device
C8051F040/1/2/3/4/5/6/7
228 Rev. 1.5
18.1. Bosch CAN Controller Operation
The CAN Controller featured in the C8051F04x family of devices is a full implementation of Bosch’s full
CAN module and fully complies with CAN specification 2.0B. A block diagram of the CAN controller is
shown in Figure 18.2. The CAN Core provides shifting (CANTX and CANRX), serial/parallel conversion of
messages, and other protocol related tasks such as transmission of data and acceptance filtering. The
message RAM stores 32 message objects which can be received or transmitted on a CAN network. The
CAN registers and message handler provide an interface for data transfer and notification between the
CAN controller and the CIP-51.
The function and use of the CAN Controller is detailed in the Bosch CAN Users Guide. The User’s Guide
should be used as a reference to configure and use the CAN controller. This Silicon Labs data sheet
describes how to access the CAN controller.
The CAN Controller is typically initialized using the following steps:
Step 1. Set the SFRPAGE register to CAN0_PAGE.
Step 2. Set the INIT the CCE bits to ‘1’ in the CAN0CN Register. See the CAN User’s Guide for bit
definitions.
Step 3. Set timing parameters in the Bit Timing Register and the BRP Extension Register.
Step 4. Initialize each message object or set it’s MsgVal bit to NOT VALID.
Step 5. Reset the INIT bit to ‘0’.
The CAN Control Register (CAN0CN), CAN Test Register (CAN0TST), and CAN Status Register
(CAN0STA) in the CAN controller can be accessed directly or indirectly via CIP-51 SFR’s. All other CAN
registers must be accessed via an indirect indexing method described in Section “18.2.5. Using
CAN0ADR, CAN0DATH, and CANDATL to Access CAN Registers” on page 232.
Figure 18.2. CAN Controller Diagram
Message Handler
REGISTERS
Message RAM
(32 Message Objects)
CAN
Core
TX RX
CAN Controller
CIP-51
MCU
Interrupt
S
F
R
's
CANTX
CANRX
C8051F04x
S
Y
S
C
L
K
CAN_CLK
(f
sys
)
BRP
Prescaler
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