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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 223
SFR Definition 17.18. P5: Port5 Data
SFR Definition 17.19. P5MDOUT: Port5 Output Mode
Bits7-0: P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P5MDOUT bit = 0). See SFR Definition
17.19.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
Note: P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-mul-
tiplexed mode). See Section “16. External Data Memory Interface and On-Chip XRAM”
on page 187 for more information about the External Memory Interface.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit
Addressable
SFR Address:
SFR Page:
0xD8
F
Bits7-0: P5MDOUT.[7:0]: Port5 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x9D
F
C8051F040/1/2/3/4/5/6/7
224 Rev. 1.5
SFR Definition 17.20. P6: Port6 Data
SFR Definition 17.21. P6MDOUT: Port6 Output Mode
Bits7-0: P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P6MDOUT bit = 0). See SFR Definition
17.21.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.
Note: P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multi-
plexed mode, or as Address[7:0] in Non-multiplexed mode). See Section “16. External
Data Memory Interface and On-Chip XRAM” on page 187 for more information about the
External Memory Interface.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit
Addressable
SFR Address:
SFR Page:
0xE8
F
Bits7-0: P6MDOUT.[7:0]: Port6 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x9E
F
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 225
SFR Definition 17.22. P7: Port7 Data
SFR Definition 17.23. P7MDOUT: Port7 Output Mode
Bits7-0: P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P7MDOUT bit = 0). See SFR Definition
17.23.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
Note: P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See Section “16. External Data Memory
Interface and On-Chip XRAM” on page 187 for more information about the External Mem-
ory Interface.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit
Addressable
SFR Address:
SFR Page:
0xF8
F
Bits7-0: P7MDOUT.[7:0]: Port7 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x9F
F
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