C8051F040/1/2/3/4/5/6/7

214 Rev. 1.5

SFR Definition 17.3. XBR2: Port I/O Crossbar Register 2

Bit7: WEAKPUD: Weak PullUp Disable Bit.

0: Weak pullups globally enabled.

1: Weak pullups globally disabled.

Bit6: XBARE: Crossbar Enable Bit.

0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode.

1: Crossbar enabled.

Bit5: UNUSED. Read = 0, Write = don't care.

Bit4: T4EXE: T4EX Input Enable Bit.

0: T4EX unavailable at Port pin.

1: T4EX routed to Port pin.

Bit3: T4E: T4 Input Enable Bit.

0: T4 unavailable at Port pin.

1: T4 routed to Port pin.

Bit2: UART1E: UART1 I/O Enable Bit.

0: UART1 I/O unavailable at Port pins.

1: UART1 TX and RX routed to 2 Port pins.

Bit1: EMIFLE: External Memory Interface Low-Port Enable Bit.

0: P0.7, P0.6, and P0.5 functions are determined by the Crossbar or the Port latches.

1: If EMI0CF.4 = ‘0’ (External Memory Interface is in Multiplexed mode)

P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) are ‘skipped’ by the Crossbar and their out-

put states are determined by the Port latches and the External Memory Interface.

1: If EMI0CF.4 = ‘1’ (External Memory Interface is in Non-multiplexed mode)

P0.7 (/WR) and P0.6 (/RD) are ‘skipped’ by the Crossbar and their output states are

determined by the Port latches and the External Memory Interface.

Bit0: CNVST0E: ADC0 External Convert Start Input Enable Bit.

0: CNVST0 for ADC0 unavailable at Port pin.

1: CNVST0 for ADC0 routed to Port pin.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

WEAKPUD XBARE — T4EXE T4E UART1E EMIFLE CNVST0E 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xE3

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 215

SFR Definition 17.4. XBR3: Port I/O Crossbar Register 3

SFR Definition 17.5. P0: Port0 Data

Bit7: CTXOUT: CAN Transmit Pin (CTX) Output Mode.

0: CTX pin output mode is configured as open-drain.

1: CTX pin output mode is configured as push-pull.

Bit6-4: Reserved

Bit3: CP2E: CP2 Output Enable Bit.

0: CP2 unavailable at Port pin.

1: CP2 routed to Port pin.

Bit2: CNVST2E: ADC2 External Convert Start Input Enable Bit (C8051F040/1/2/3 only).

0: CNVST2 for ADC2 unavailable at Port pin.

1: CNVST2 for ADC2 routed to Port pin.

Bit1: T3EXE: T3EX Input Enable Bit.

0: T3EX unavailable at Port pin.

1: T3EX routed to Port pin.

Bit0: T3E: T3 Input Enable Bit.

0: T3 unavailable at Port pin.

1: T3 routed to Port pin.

R/W R R R R/W R/W R/W R/W Reset Value

CTXOUT — — — CP2E CNVST2E T3EXE T3E 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xE4

Bits7-0: P0.[7:0]: Port0 Output Latch Bits.

(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)

0: Logic Low Output.

1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).

(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).

0: P0.n pin is logic low.

1: P0.n pin is logic high.

Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory

Interface. See Section “16. External Data Memory Interface and On-Chip XRAM” on

page 187 for more information. See also SFR Definition 17.3 for information about configur-

ing the Crossbar for External Memory accesses.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x80

All Pages

C8051F040/1/2/3/4/5/6/7

216 Rev. 1.5

SFR Definition 17.6. P0MDOUT: Port0 Output Mode

SFR Definition 17.7. P1: Port1 Data

Bits7-0: P0MDOUT.[7:0]: Port0 Output Mode Bits.

0: Port Pin output mode is configured as Open-Drain.

1: Port Pin output mode is configured as Push-Pull.

Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are

always configured as Open-Drain when they appear on Port pins.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xA4

Bits7-0: P1.[7:0]: Port1 Output Latch Bits.

(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)

0: Logic Low Output.

1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).

(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).

0: P1.n pin is logic low.

1: P1.n pin is logic high.

Notes:

1. P1.[7:0] can be configured as inputs to ADC1 as AIN1.[7:0], in which case they are ‘skipped’

by the Crossbar assignment process and their digital input paths are disabled, depending on

P1MDIN (See SFR Definition 17.8). Note that in analog mode, the output mode of the pin is

determined by the Port 1 latch and P1MDOUT (SFR Definition 17.9). See Section “7. 8-Bit

ADC (ADC2, C8051F040/1/2/3 Only)” on page 91 for more information about ADC2.

2. P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-mul-

tiplexed mode). See Section “16. External Data Memory Interface and On-Chip XRAM”

on page 187 for more information about the External Memory Interface.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x90

All Pages

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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