C8051F040/1/2/3/4/5/6/7
210 Rev. 1.5
17.1.7. Crossbar Pin Assignment Example
In this example (Figure 17.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus,
UART1, /INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to oper-
ate in Multiplexed mode and to appear on the Low ports. Further, we configure P1.2, P1.3, and P1.4 for
Analog Input mode so that the voltages at these pins can be measured by ADC2. The configuration steps
are as follows:
1. XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, INT0E = 1, INT1E =
1, and EMIFLE = 1. Thus: XBR0 = 0x05, XBR1 = 0x14, and XBR2 = 0x02.
2. We configure the External Memory Interface to use Multiplexed mode and to appear on the
Lo
w ports. PRTSEL = 0, EMD2 = 0.
3. We configure the desired Port 1 pins to Analog Input mode by se
tting P1MDIN to 0xE3 (P1.4,
P1.3, and P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0).
4. We enable the Crossbar by setting XBARE =
1: XBR2 = 0x42.
- UART0 has the highest priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0.
- The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to
SCL.
- UART1 is next in priority order, so P0.4 is assigne
d to TX1. Because the External Memory
Interface is selected on the lower Ports, EMIFLE = 1, which causes the Crossbar to skip
P0.6 (/RD) and P0.7 (/WR). Because the External Memory Interface is configured in Multi-
plexed mode, the Crossbar will als
o skip P0.5 (ALE). RX1 is assigned to the next non-
skipped pin, which in this case is P1.0.
- /INT0 is next in priority order, so it is assigned to P1.1.
- P1MDIN is set to 0xE3, which configures P1.2, P1.3,
and P1.4 as Analog Inputs, causing
the Crossbar to skip these pins.
- /INT1 is next in priority order, so it is assign
ed to the next non-skipped pin, which is P1.5.
- The External Memory Interface will drive Ports 2 and 3 (denoted by red dots in
Figure 17.6) during the execution of an off-chip MOVX instruction.
5. We set the UART0 TX pin (TX0, P0.0) and UART1 TX pin (TX1, P0.4) outputs to Push-Pull by
setting P0MD
OUT = 0x11.
6. We configure all EMIF-controlled pins to push-pull output mode by setting P0MDOUT |= 0xE0;
P2MDOUT = 0xFF; P3MDOUT = 0xFF.
7. We explicitly disable th
e output drivers on the 3 Analog Input pins by setting P1MDOUT =
0x00 (configure outputs to Open-Drain) and P1 = 0xFF (a logic 1 selects the high-impedance
st
ate).
