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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
190 Rev. 1.5
SFR Definition 16.2. EMI0CF: External Memory Configuration
Bits7-6: Unused. Read = 00b. Write = don’t care.
Bit5: PRTSEL: EMIF Port Select.
0: EMIF active on P0-P3.
1: EMIF active on P4-P7.
Bit4: EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
Bits3-2: EMD1-0: EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-
chip memory space.
01: Split Mode without Bank Select: Accesses below the 4k boundary are directed on-chip.
Accesses above the 4k boundary are directed off-chip. 8-bit off-chip MOVX operations
use the current contents of the Address High port latches to resolve upper address byte.
Note that in order to access off-chip space, EMI0CN must be set to a page that is not
contained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 4k boundary are directed on-chip.
Accesses above the 4k boundary are directed off-chip. 8-bit off-chip MOVX operations
use the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the
CPU.
Bits1-0: EALE1-0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 1).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - PRTSEL EMD2 EMD1 EMD0 EALE1 EALE0 00000011
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xA3
0
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 191
16.4. Multiplexed and Non-multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
16.4.1. Multiplexed Configuration
In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in
Figure 16.1.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are pre-
sented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time /RD or /WR is asserted.
See Section “16.6.2. Multiplexed Mode” on page 199 for more information.
Figure 16.1. Multiplexed Configuration Example
ADDRESS/DATA BUS
ADDRESS BUS
E
M
I
F
A[15:8]
AD[7:0]
/WR
/RD
ALE
64K X 8
SRAM
OE
WE
I/O[7:0]
74HC373
G
DQ
A[15:8]
A[7:0]
CE
V
DD
8
(Optional)
C8051F040/1/2/3/4/5/6/7
192 Rev. 1.5
16.4.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-
multiplexed Configuration is shown in Figure 16.2. See Section “16.6.1. Non-multiplexed Mode” on
page 196 for more information about Non-multiplexed operation.
Figure 16.2. Non-multiplexed Configuration Example
ADDRESS BUS
E
M
I
F
A[15:0]
64K X 8
SRAM
A[15:0]
DATA BUSD[7:0] I/O[7:0]
V
DD
8
/WR
/RD OE
WE
CE
(Optional)
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