C8051F040/1/2/3/4/5/6/7

Rev. 1.5 187

16. External Data Memory Interface and On-Chip XRAM

The C8051F04x MCUs include 4 kB of on-chip RAM mapped into the external data memory space

(XRAM), as well as an External Data Memory Interface which can be used to access off-chip memories

and memory-mapped devices connected to the GPIO ports. The external memory space may be accessed

using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect

addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as

@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Reg-

ister (EMI0CN, shown in SFR Definition 16.1). Note: the MOVX instruction can also be used for writing to

the Flash memory. See Section “15. Flash Memory” on page 179 for details. The MOVX instruction

accesses XRAM by default. The EMIF can be configured to appear on the lower GPIO Ports (P0-P3) or the

upper GPIO Ports (P4-P7).

16.1. Accessing XRAM

The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,

both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit

ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM

address. Examples of both of these methods are given below.

16.1.1. 16-Bit MOVX Example

The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the

DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the

accumulator A:

MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234)

MOVX A, @DPTR ; load contents of 0x1234 into accumulator A



The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,

the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and

DPL, which contains the lower 8-bits of DPTR.

16.1.2. 8-Bit MOVX Example

The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits

of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the

effective address to be accessed. The following series of instructions read the contents of the byte at

address 0x1234 into the accumulator A.

MOV EMI0CN, #12h ; load high byte of address into EMI0CN

MOV R0, #34h ; load low byte of address into R0 (or R1)

MOVX a, @R0 ; load contents of 0x1234 into accumulator A

C8051F040/1/2/3/4/5/6/7

188 Rev. 1.5

16.2. Configuring the External Memory Interface

Configuring the External Memory Interface consists of five steps:

1. Select EMIF on Low Ports (P3, P2, P1, and P0) or High Ports (P7, P6, P5, and P4).

2. Configure the Output Modes of the port pins as either push-pull or open-drain.

3. Select Multiplexed mode o

r Non-multiplexed mode.

4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank

selec

t, or off-chip only).

5. Set up timing to interface with off-chip memory or peripherals.

Each of these five steps is explained in detail in the following s

ections. The Port selection, Multiplexed

mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 16.2.

16.3. Port Selection and Configuration

The External Memory Interface can appear on Ports 3, 2, 1, and 0 (C8051F04x devices) or on Ports 7, 6,

5, and 4 (C8051F040/2/4/6 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the

lower Ports are selected, the EMIFLE bit (XBR2.1) must be set to a ‘1’ so that the Crossbar will skip over

P0.7 (/WR), P0.6 (/RD), and, if multiplexed mode is selected, P0.5 (ALE). For more information about the

configuring the Crossbar, see Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on

page 204.

The External Memory Interface claims the associated Port pins for memory operations ONLY during the

execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port

pins reverts to the Port latches or to the Crossbar (on Ports 3, 2, 1, and 0). See Section “17. Port Input/

Output” on page 203 for more information about the Crossbar and Port operation and configuration. The

Port latches should be explicitly configured as push-pull to ‘park’ the External Memory Interface

pins in a dormant state, most commonly by setting them to a logic 1.

During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-

ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output

mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the

External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,

the output modes of all EMIF pins should be configured for push-pull mode. See Section

“17.1.2. Configuring the Output Modes of the Port Pins” on page 206.

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 189

SFR Definition 16.1. EMI0CN: External Memory Interface Control

Bits7-0: PGSEL[7:0]: XRAM Page Select Bits.

The XRAM Page Select Bits provide the high byte of the 16-bit external data memory

address when using an 8-bit MOVX command, effectively selecting a 256-byte page of

RAM.

0x00: 0x0000 to 0x00FF

0x01: 0x0100 to 0x01FF

...

0xFE: 0xFE00 to 0xFEFF

0xFF: 0xFF00 to 0xFFFF

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xA2

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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