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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 19
1. System Overview
The C8051F04x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital
I/O pins (C8051F040/2/4/6) or 32 digital I/O pins (C8051F041/3/5/7), and an integrated CAN 2.0B control-
ler. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.
High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
Controller Area Network (CAN 2.0B)
Controller with 32 message objects, each with its own indentifier
mask.
In-system, full-speed, non-intrusive debug interface (on-chip)
True 12-bit (C8051F040/1) or 10-bit (C8051F042/3/4/5/6/7) 100 ksps 8-channel ADC with PGA and
analog multiplexer
High Voltage Difference Amplifier input to the 12/10-bit ADC (60 V Peak-to-Peak) with programmable
ga
in.
True 8-bit 500 ksps 8-channel ADC with PGA and analog
multiplexer (C8051F040/1/2/3)
Two 12-bit DACs with programmable update scheduling (C8051F040/1/2/3)
•64 kB (C8051F040/1/2/3/4/5) or
32 kB (C8051F046/7) of in-system programmable Flash memory
4352 (4096 + 256) bytes of on-chip RAM
External Data Memory Interface with 64 kB address space
SPI, SMBus/I
2
C, and (2) UART serial interfaces implemented in hardware
Five general purpose 16-bit Timers
Programmable Counter/Timer Array with six capture/compare modules
On-chip Watchdog Timer, V
DD
Monitor, and Temperature Sensor
With on-chip V
DD
monitor, Watchdog Timer, and clock oscillator, the C8051F04x family of devices are truly
stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and con-
figured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing non-volatile
data storage, and also allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit pro-
gramming and debugging using the production MCU installed in the final application. This debug system
supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single
stepping, Run, and Halt commands. All analog and digital peripherals are fully functional while debugging
using JTAG.
Each MCU is specified for 2.7 V to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F040/2/4/6 are avail-
able in a 100-pin TQFP and the C8051F041/3/5/7 are available in a 64-pin TQFP.
C8051F040/1/2/3/4/5/6/7
20 Rev. 1.5
Table 1.1. Product Selection Guide
Ordering Part Number
MIPS (Peak)
Flash Memory
RAM
External Memory Interface
SMBus/I
2
C and SPI
CAN
UARTS
Timers (16-bit)
Programmable Counter Array
Digital Port I/O’s
12-bit 100ksps ADC
10-bit 100ksps ADC
8-bit 500 ksps ADC Inputs
High Voltage Diff Amp
Voltage Reference
Temperature Sensor
DAC Resolution (bits)
DAC Outputs
Analog Comparators
Lead-free (RoHS Compliant)
Package
C8051F040 25 64 kB 4352
2 5
64
- 8
12 2 3 - 100TQFP
C8051F040-GQ 25 64 kB 4352
2 5
64
- 8
12 2 3
100TQFP
C8051F041 25 64 kB 4352
2 5
32
- 8
12 2 3 - 64TQFP
C8051F041-GQ 25 64 kB 4352
2 5
32
- 8
12 2 3
64TQFP
C8051F042 25 64 kB 4352
2 5
64 -
8
12 2 3 - 100TQFP
C8051F042-GQ 25 64 kB 4352
2 5
64 -
8
12 2 3
100TQFP
C8051F043 25 64 kB 4352
2 5
32 -
8
12 2 3 - 64TQFP
C8051F043-GQ 25 64 kB 4352
2 5
32 -
8
12 2 3
64TQFP
C8051F044 25 64 kB 4352
2 5
64 -
3 - 100TQFP
C8051F044-GQ 25 64 kB 4352
2 5
64 -
3
100TQFP
C8051F045 25 64
kB 4352
2 5
32 -
3 - 64TQFP
C8051F045-GQ 25 64 kB 4352
2 5
32 -
3
64TQFP
C8051F046 25 32 kB 4352
2 5
64 -
3 - 100TQFP
C8051F046-GQ 25 32 kB 4352
2 5
64 -
3
100TQFP
C8051F047 25 32 kB 4352
2 5
32 -
3 - 64TQFP
C8051F047-GQ 25 32 kB 4352
2 5
32 -
3
64TQFP
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 21
Figure 1.1. C8051F040/2 Block Diagram
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
VDD
VDD
VDD
DGND
DGND
DGND
/RST
XTAL1
XTAL2
P2.0
P2.7
P0.0
P0.7
DAC1
DAC1
(12-Bit)
VREF
DAC0
(12-Bit)
AIN0.0
DAC0
VREF
UART0
8:1
MONEN
WDT
VREFD
VREF0
P7 Latch
P5 Latch
P6 Latch
P5.0/A8
P5.7/A51
P5
DRV
P6.0/A0
P6.7/A7
P6
DRV
P4
DRV
P4.5/ALE
P4.6/RD
P4.7/WR
P4.4
Addr [7:0]
Addr [15:8]
Ctrl Latch
Data Latch
A
M
U
X
8:2
HVAIN+
HVAIN-
HVREF
HVCAP
HVAMP
TEMP
SENSOR
P0
Drv
P1
Drv
P2
Drv
P3
Drv
Port
0,1,2,3
&4
Latches
CAN
2.0B
CANTX
8
0
5
1
C
o
r
e
Reset
A
M
U
X
Prog
Gain
ADC
100 ksps
(12 or 10-
Bit)
32x136
CANRAM
256 byte
RAM
4 kB
RAM
P3.0
P3.7
P1.0
P1.7
64 kB
Flash
System
Clock
Internal
Oscillator
External
Oscillator
Circuit
V
DD
Monitor
C
R
O
S
S
B
A
R
Data [7:0]
Address [15:0]
Bus Control
Digital Power
Memories
Port 4 <from crossbar>
A
M
U
X
Prog
Gain
ADC
500 ksps
(8-Bit)
VREF2
P4.0
SFR Bus
P7
DRV
P7.0/D0
P7.7/D7
AV+
Debug HW
Boundary Scan
JTAG
Logic
TCK
TMS
TDI
TDO
AGND
AGND
AGND
AV+
AV+
Analog Power
P2.7
P2.6
+
-
CP0
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
AIN0.3
AIN0.2
AIN0.1
CANRX
External Memory Data
Bus
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